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https://github.com/smaeul/u-boot.git
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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
133 lines
2.4 KiB
C
133 lines
2.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 MediaTek Inc.
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* Author: Ryder Lee <ryder.lee@mediatek.com>
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*/
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#include <clk.h>
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#include <common.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <init.h>
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#include <log.h>
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#include <ram.h>
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#include <asm/arch/misc.h>
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#include <asm/global_data.h>
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#include <asm/sections.h>
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#include <dm/uclass.h>
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#include <linux/bitops.h>
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#include <linux/io.h>
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#include <dt-bindings/clock/mt7629-clk.h>
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#define L2_CFG_BASE 0x10200000
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#define L2_CFG_SIZE 0x1000
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#define L2_SHARE_CFG_MP0 0x7f0
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#define L2_SHARE_MODE_OFF BIT(8)
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DECLARE_GLOBAL_DATA_PTR;
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int mtk_pll_early_init(void)
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{
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unsigned long pll_rates[] = {
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[CLK_APMIXED_ARMPLL] = 1250000000,
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[CLK_APMIXED_MAINPLL] = 1120000000,
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[CLK_APMIXED_UNIV2PLL] = 1200000000,
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[CLK_APMIXED_ETH1PLL] = 500000000,
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[CLK_APMIXED_ETH2PLL] = 700000000,
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[CLK_APMIXED_SGMIPLL] = 650000000,
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};
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struct udevice *dev;
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int ret, i;
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ret = uclass_get_device_by_driver(UCLASS_CLK,
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DM_DRIVER_GET(mtk_clk_apmixedsys), &dev);
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if (ret)
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return ret;
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/* configure default rate then enable apmixedsys */
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for (i = 0; i < ARRAY_SIZE(pll_rates); i++) {
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struct clk clk = { .id = i, .dev = dev };
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ret = clk_set_rate(&clk, pll_rates[i]);
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if (ret)
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return ret;
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ret = clk_enable(&clk);
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if (ret)
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return ret;
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}
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/* setup mcu bus */
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ret = uclass_get_device_by_driver(UCLASS_SYSCON,
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DM_DRIVER_GET(mtk_mcucfg), &dev);
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if (ret)
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return ret;
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return 0;
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}
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int mtk_soc_early_init(void)
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{
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struct udevice *dev;
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int ret;
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/* initialize early clocks */
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ret = mtk_pll_early_init();
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if (ret)
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return ret;
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ret = uclass_first_device_err(UCLASS_RAM, &dev);
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if (ret)
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return ret;
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return 0;
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}
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int mach_cpu_init(void)
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{
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void __iomem *base;
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base = ioremap(L2_CFG_BASE, L2_CFG_SIZE);
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/* disable L2C shared mode */
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writel(L2_SHARE_MODE_OFF, base + L2_SHARE_CFG_MP0);
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return 0;
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}
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int dram_init(void)
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{
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struct ram_info ram;
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struct udevice *dev;
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int ret;
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ret = uclass_first_device_err(UCLASS_RAM, &dev);
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if (ret)
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return ret;
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ret = ram_get_info(dev, &ram);
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if (ret)
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return ret;
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debug("RAM init base=%lx, size=%x\n", ram.base, ram.size);
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gd->ram_size = ram.size;
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return 0;
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}
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int print_cpuinfo(void)
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{
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void __iomem *chipid;
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u32 hwcode, swver;
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chipid = ioremap(VER_BASE, VER_SIZE);
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hwcode = readl(chipid + APHW_CODE);
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swver = readl(chipid + APSW_VER);
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printf("CPU: MediaTek MT%04x E%d\n", hwcode, (swver & 0xf) + 1);
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return 0;
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}
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