mirror of
https://github.com/smaeul/u-boot.git
synced 2025-10-22 00:28:15 +01:00
d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
112 lines
1.9 KiB
C
112 lines
1.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* (C) Copyright 2016 Vladimir Zapolskiy <vz@mleia.com>
|
|
* (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <command.h>
|
|
#include <cpu_func.h>
|
|
#include <asm/cache.h>
|
|
#include <asm/io.h>
|
|
#include <asm/processor.h>
|
|
#include <asm/system.h>
|
|
|
|
#define CACHE_VALID 1
|
|
#define CACHE_UPDATED 2
|
|
|
|
static inline void cache_wback_all(void)
|
|
{
|
|
unsigned long addr, data, i, j;
|
|
|
|
for (i = 0; i < CACHE_OC_NUM_ENTRIES; i++) {
|
|
for (j = 0; j < CACHE_OC_NUM_WAYS; j++) {
|
|
addr = CACHE_OC_ADDRESS_ARRAY
|
|
| (j << CACHE_OC_WAY_SHIFT)
|
|
| (i << CACHE_OC_ENTRY_SHIFT);
|
|
data = inl(addr);
|
|
if (data & CACHE_UPDATED) {
|
|
data &= ~CACHE_UPDATED;
|
|
outl(data, addr);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
#define CACHE_ENABLE 0
|
|
#define CACHE_DISABLE 1
|
|
|
|
static int cache_control(unsigned int cmd)
|
|
{
|
|
unsigned long ccr;
|
|
|
|
jump_to_P2();
|
|
ccr = inl(CCR);
|
|
|
|
if (ccr & CCR_CACHE_ENABLE)
|
|
cache_wback_all();
|
|
|
|
if (cmd == CACHE_DISABLE)
|
|
outl(CCR_CACHE_STOP, CCR);
|
|
else
|
|
outl(CCR_CACHE_INIT, CCR);
|
|
back_to_P1();
|
|
|
|
return 0;
|
|
}
|
|
|
|
void flush_dcache_range(unsigned long start, unsigned long end)
|
|
{
|
|
u32 v;
|
|
|
|
start &= ~(L1_CACHE_BYTES - 1);
|
|
for (v = start; v < end; v += L1_CACHE_BYTES) {
|
|
asm volatile ("ocbp %0" : /* no output */
|
|
: "m" (__m(v)));
|
|
}
|
|
}
|
|
|
|
void invalidate_dcache_range(unsigned long start, unsigned long end)
|
|
{
|
|
u32 v;
|
|
|
|
start &= ~(L1_CACHE_BYTES - 1);
|
|
for (v = start; v < end; v += L1_CACHE_BYTES) {
|
|
asm volatile ("ocbi %0" : /* no output */
|
|
: "m" (__m(v)));
|
|
}
|
|
}
|
|
|
|
void flush_cache(unsigned long addr, unsigned long size)
|
|
{
|
|
flush_dcache_range(addr , addr + size);
|
|
}
|
|
|
|
void icache_enable(void)
|
|
{
|
|
cache_control(CACHE_ENABLE);
|
|
}
|
|
|
|
void icache_disable(void)
|
|
{
|
|
cache_control(CACHE_DISABLE);
|
|
}
|
|
|
|
int icache_status(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
void dcache_enable(void)
|
|
{
|
|
}
|
|
|
|
void dcache_disable(void)
|
|
{
|
|
}
|
|
|
|
int dcache_status(void)
|
|
{
|
|
return 0;
|
|
}
|