mirror of
https://github.com/smaeul/u-boot.git
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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
150 lines
3.0 KiB
C
150 lines
3.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2021 NXP
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*/
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#include <common.h>
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#include <init.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <errno.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx8ulp-pins.h>
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#include <dm/uclass.h>
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#include <dm/device.h>
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#include <dm/uclass-internal.h>
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#include <dm/device-internal.h>
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#include <dm/lists.h>
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#include <asm/arch/ddr.h>
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#include <asm/arch/rdc.h>
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#include <asm/arch/upower.h>
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#include <asm/mach-imx/ele_api.h>
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#include <asm/sections.h>
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DECLARE_GLOBAL_DATA_PTR;
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void spl_dram_init(void)
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{
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/* Reboot in dual boot setting no need to init ddr again */
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bool ddr_enable = pcc_clock_is_enable(5, LPDDR4_PCC5_SLOT);
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if (!ddr_enable) {
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init_clk_ddr();
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ddr_init(&dram_timing);
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} else {
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/* reinit pfd/pfddiv and lpavnic except pll4*/
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cgc2_pll4_init(false);
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}
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}
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u32 spl_boot_device(void)
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{
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return BOOT_DEVICE_BOOTROM;
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}
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int power_init_board(void)
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{
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if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE)) {
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/* Set buck3 to 0.9v LD */
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upower_pmic_i2c_write(0x22, 0x18);
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} else if (IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) {
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/* Set buck3 to 1.0v ND */
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upower_pmic_i2c_write(0x22, 0x20);
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} else {
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/* Set buck3 to 1.1v OD */
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upower_pmic_i2c_write(0x22, 0x28);
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}
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return 0;
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}
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void display_ele_fw_version(void)
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{
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u32 fw_version, sha1, res;
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int ret;
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ret = ele_get_fw_version(&fw_version, &sha1, &res);
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if (ret) {
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printf("ele get firmware version failed %d, 0x%x\n", ret, res);
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} else {
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printf("ELE firmware version %u.%u.%u-%x",
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(fw_version & (0x00ff0000)) >> 16,
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(fw_version & (0x0000ff00)) >> 8,
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(fw_version & (0x000000ff)), sha1);
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((fw_version & (0x80000000)) >> 31) == 1 ? puts("-dirty\n") : puts("\n");
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}
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}
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void spl_board_init(void)
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{
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u32 res;
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int ret;
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ret = imx8ulp_dm_post_init();
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if (ret)
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return;
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board_early_init_f();
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preloader_console_init();
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puts("Normal Boot\n");
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display_ele_fw_version();
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/* After AP set iomuxc0, the i2c can't work, Need M33 to set it now */
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/* Load the lposc fuse to work around ROM issue. The fuse depends on S400 to read. */
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if (is_soc_rev(CHIP_REV_1_0))
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load_lposc_fuse();
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upower_init();
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power_init_board();
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clock_init_late();
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/* This must place after upower init, so access to MDA and MRC are valid */
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/* Init XRDC MDA */
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xrdc_init_mda();
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/* Init XRDC MRC for VIDEO, DSP domains */
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xrdc_init_mrc();
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xrdc_init_pdac_msc();
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/* DDR initialization */
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spl_dram_init();
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/* Call it after PS16 power up */
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set_lpav_qos();
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/* Enable A35 access to the CAAM */
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ret = ele_release_caam(0x7, &res);
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if (ret)
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printf("ele release caam failed %d, 0x%x\n", ret, res);
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/*
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* RNG start only available on the A1 soc revision.
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* Check some JTAG register for the SoC revision.
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*/
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if (!is_soc_rev(CHIP_REV_1_0)) {
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ret = ele_start_rng();
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if (ret)
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printf("Fail to start RNG: %d\n", ret);
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}
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}
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void board_init_f(ulong dummy)
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{
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/* Clear the BSS. */
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memset(__bss_start, 0, __bss_end - __bss_start);
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timer_init();
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arch_cpu_init();
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board_init_r(NULL, 0);
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}
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