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https://github.com/smaeul/u-boot.git
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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
165 lines
3.1 KiB
C
165 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2014
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* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
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*/
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#include <common.h>
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#include <linux/delay.h>
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#include <miiphy.h>
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#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
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#include <gdsys_fpga.h>
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#else
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#include <fdtdec.h>
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#include <dm.h>
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#include <regmap.h>
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#endif
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#include "ihs_mdio.h"
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#ifndef CONFIG_GDSYS_LEGACY_DRIVERS
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enum {
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REG_MDIO_CONTROL = 0x0,
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REG_MDIO_ADDR_DATA = 0x2,
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REG_MDIO_RX_DATA = 0x4,
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};
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static inline u16 read_reg(struct udevice *fpga, uint base, uint addr)
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{
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struct regmap *map;
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u8 *ptr;
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regmap_init_mem(dev_ofnode(fpga), &map);
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ptr = regmap_get_range(map, 0);
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return in_le16((u16 *)(ptr + base + addr));
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}
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static inline void write_reg(struct udevice *fpga, uint base, uint addr,
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u16 val)
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{
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struct regmap *map;
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u8 *ptr;
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regmap_init_mem(dev_ofnode(fpga), &map);
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ptr = regmap_get_range(map, 0);
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out_le16((u16 *)(ptr + base + addr), val);
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}
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#endif
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static inline u16 read_control(struct ihs_mdio_info *info)
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{
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u16 val;
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#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
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FPGA_GET_REG(info->fpga, mdio.control, &val);
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#else
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val = read_reg(info->fpga, info->base, REG_MDIO_CONTROL);
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#endif
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return val;
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}
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static inline void write_control(struct ihs_mdio_info *info, u16 val)
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{
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#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
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FPGA_SET_REG(info->fpga, mdio.control, val);
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#else
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write_reg(info->fpga, info->base, REG_MDIO_CONTROL, val);
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#endif
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}
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static inline void write_addr_data(struct ihs_mdio_info *info, u16 val)
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{
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#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
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FPGA_SET_REG(info->fpga, mdio.address_data, val);
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#else
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write_reg(info->fpga, info->base, REG_MDIO_ADDR_DATA, val);
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#endif
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}
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static inline u16 read_rx_data(struct ihs_mdio_info *info)
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{
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u16 val;
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#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
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FPGA_GET_REG(info->fpga, mdio.rx_data, &val);
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#else
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val = read_reg(info->fpga, info->base, REG_MDIO_RX_DATA);
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#endif
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return val;
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}
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static int ihs_mdio_idle(struct mii_dev *bus)
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{
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struct ihs_mdio_info *info = bus->priv;
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u16 val;
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unsigned int ctr = 0;
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do {
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val = read_control(info);
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udelay(100);
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if (ctr++ > 10)
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return -1;
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} while (!(val & (1 << 12)));
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return 0;
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}
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static int ihs_mdio_reset(struct mii_dev *bus)
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{
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ihs_mdio_idle(bus);
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return 0;
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}
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static int ihs_mdio_read(struct mii_dev *bus, int addr, int dev_addr,
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int regnum)
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{
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struct ihs_mdio_info *info = bus->priv;
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u16 val;
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ihs_mdio_idle(bus);
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write_control(info,
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((addr & 0x1f) << 5) | (regnum & 0x1f) | (2 << 10));
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/* wait for rx data available */
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udelay(100);
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val = read_rx_data(info);
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return val;
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}
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static int ihs_mdio_write(struct mii_dev *bus, int addr, int dev_addr,
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int regnum, u16 value)
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{
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struct ihs_mdio_info *info = bus->priv;
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ihs_mdio_idle(bus);
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write_addr_data(info, value);
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write_control(info, ((addr & 0x1f) << 5) | (regnum & 0x1f) | (1 << 10));
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return 0;
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}
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int ihs_mdio_init(struct ihs_mdio_info *info)
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{
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struct mii_dev *bus = mdio_alloc();
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if (!bus) {
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printf("Failed to allocate FSL MDIO bus\n");
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return -1;
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}
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bus->read = ihs_mdio_read;
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bus->write = ihs_mdio_write;
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bus->reset = ihs_mdio_reset;
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strcpy(bus->name, info->name);
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bus->priv = info;
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return mdio_register(bus);
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}
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