mirror of
https://github.com/smaeul/u-boot.git
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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
272 lines
8.3 KiB
C
272 lines
8.3 KiB
C
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Clock drivers for Qualcomm QCS404
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*
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* (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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#include <dt-bindings/clock/qcom,gcc-qcs404.h>
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#include "clock-qcom.h"
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/* Clocks: (from CLK_CTL_BASE) */
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#define GPLL0_STATUS (0x21000)
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#define GPLL1_STATUS (0x20000)
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#define APCS_GPLL_ENA_VOTE (0x45000)
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#define APCS_CLOCK_BRANCH_ENA_VOTE (0x45004)
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/* BLSP1 AHB clock (root clock for BLSP) */
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#define BLSP1_AHB_CBCR 0x1008
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/* Uart clock control registers */
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#define BLSP1_UART2_BCR (0x3028)
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#define BLSP1_UART2_APPS_CBCR (0x302C)
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#define BLSP1_UART2_APPS_CMD_RCGR (0x3034)
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/* I2C controller clock control registerss */
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#define BLSP1_QUP0_I2C_APPS_CBCR (0x6028)
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#define BLSP1_QUP0_I2C_APPS_CMD_RCGR (0x602C)
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#define BLSP1_QUP1_I2C_APPS_CBCR (0x2008)
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#define BLSP1_QUP1_I2C_APPS_CMD_RCGR (0x200C)
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#define BLSP1_QUP2_I2C_APPS_CBCR (0x3010)
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#define BLSP1_QUP2_I2C_APPS_CMD_RCGR (0x3000)
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#define BLSP1_QUP3_I2C_APPS_CBCR (0x4020)
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#define BLSP1_QUP3_I2C_APPS_CMD_RCGR (0x4000)
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#define BLSP1_QUP4_I2C_APPS_CBCR (0x5020)
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#define BLSP1_QUP4_I2C_APPS_CMD_RCGR (0x5000)
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/* SD controller clock control registers */
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#define SDCC_BCR(n) (((n) * 0x1000) + 0x41000)
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#define SDCC_CMD_RCGR(n) (((n + 1) * 0x1000) + 0x41004)
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#define SDCC_APPS_CBCR(n) (((n) * 0x1000) + 0x41018)
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#define SDCC_AHB_CBCR(n) (((n) * 0x1000) + 0x4101C)
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/* USB-3.0 controller clock control registers */
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#define SYS_NOC_USB3_CBCR (0x26014)
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#define USB30_BCR (0x39000)
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#define USB3PHY_BCR (0x39008)
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#define USB30_MASTER_CBCR (0x3900C)
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#define USB30_SLEEP_CBCR (0x39010)
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#define USB30_MOCK_UTMI_CBCR (0x39014)
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#define USB30_MOCK_UTMI_CMD_RCGR (0x3901C)
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#define USB30_MOCK_UTMI_CFG_RCGR (0x39020)
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#define USB30_MASTER_CMD_RCGR (0x39028)
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#define USB2A_PHY_SLEEP_CBCR (0x4102C)
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#define USB_HS_PHY_CFG_AHB_CBCR (0x41030)
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/* ETH controller clock control registers */
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#define ETH_PTP_CBCR (0x4e004)
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#define ETH_RGMII_CBCR (0x4e008)
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#define ETH_SLAVE_AHB_CBCR (0x4e00c)
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#define ETH_AXI_CBCR (0x4e010)
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#define EMAC_PTP_CMD_RCGR (0x4e014)
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#define EMAC_CMD_RCGR (0x4e01c)
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/* GPLL0 clock control registers */
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#define GPLL0_STATUS_ACTIVE BIT(31)
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#define CFG_CLK_SRC_GPLL1 BIT(8)
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#define GPLL1_STATUS_ACTIVE BIT(31)
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static struct vote_clk gcc_blsp1_ahb_clk = {
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.cbcr_reg = BLSP1_AHB_CBCR,
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.ena_vote = APCS_CLOCK_BRANCH_ENA_VOTE,
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.vote_bit = BIT(10) | BIT(5) | BIT(4),
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};
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static struct pll_vote_clk gpll0_vote_clk = {
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.status = GPLL0_STATUS,
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.status_bit = GPLL0_STATUS_ACTIVE,
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.ena_vote = APCS_GPLL_ENA_VOTE,
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.vote_bit = BIT(0),
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};
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static struct pll_vote_clk gpll1_vote_clk = {
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.status = GPLL1_STATUS,
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.status_bit = GPLL1_STATUS_ACTIVE,
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.ena_vote = APCS_GPLL_ENA_VOTE,
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.vote_bit = BIT(1),
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};
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static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate)
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{
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struct msm_clk_priv *priv = dev_get_priv(clk->dev);
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switch (clk->id) {
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case GCC_BLSP1_UART2_APPS_CLK:
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/* UART: 1843200Hz for a fixed 115200 baudrate (19200000 * (12/125)) */
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clk_rcg_set_rate_mnd(priv->base, BLSP1_UART2_APPS_CMD_RCGR, 0, 12, 125,
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CFG_CLK_SRC_CXO, 16);
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clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR);
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return 1843200;
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case GCC_SDCC1_APPS_CLK:
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/* SDCC1: 200MHz */
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clk_rcg_set_rate_mnd(priv->base, SDCC_CMD_RCGR(0), 7, 0, 0,
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CFG_CLK_SRC_GPLL0, 8);
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clk_enable_gpll0(priv->base, &gpll0_vote_clk);
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clk_enable_cbc(priv->base + SDCC_APPS_CBCR(1));
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return rate;
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case GCC_ETH_RGMII_CLK:
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if (rate == 250000000)
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clk_rcg_set_rate_mnd(priv->base, EMAC_CMD_RCGR, 3, 0, 0,
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CFG_CLK_SRC_GPLL1, 8);
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else if (rate == 125000000)
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clk_rcg_set_rate_mnd(priv->base, EMAC_CMD_RCGR, 7, 0, 0,
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CFG_CLK_SRC_GPLL1, 8);
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else if (rate == 50000000)
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clk_rcg_set_rate_mnd(priv->base, EMAC_CMD_RCGR, 19, 0, 0,
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CFG_CLK_SRC_GPLL1, 8);
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else if (rate == 5000000)
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clk_rcg_set_rate_mnd(priv->base, EMAC_CMD_RCGR, 3, 1, 50,
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CFG_CLK_SRC_GPLL1, 8);
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return rate;
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}
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/* There is a bug only seeming to affect this board where the MMC driver somehow calls
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* clk_set_rate() on a clock with id 0 which is associated with the qcom_clk device.
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* The only clock with ID 0 is the xo_board clock which should not be associated with
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* this device...
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*/
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log_debug("Unknown clock id %ld\n", clk->id);
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return 0;
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}
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static int qcs404_clk_enable(struct clk *clk)
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{
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struct msm_clk_priv *priv = dev_get_priv(clk->dev);
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switch (clk->id) {
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case GCC_USB30_MASTER_CLK:
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clk_enable_cbc(priv->base + USB30_MASTER_CBCR);
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clk_rcg_set_rate_mnd(priv->base, USB30_MASTER_CMD_RCGR, 7, 0, 0,
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CFG_CLK_SRC_GPLL0, 8);
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break;
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case GCC_SYS_NOC_USB3_CLK:
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clk_enable_cbc(priv->base + SYS_NOC_USB3_CBCR);
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break;
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case GCC_USB30_SLEEP_CLK:
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clk_enable_cbc(priv->base + USB30_SLEEP_CBCR);
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break;
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case GCC_USB30_MOCK_UTMI_CLK:
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clk_enable_cbc(priv->base + USB30_MOCK_UTMI_CBCR);
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break;
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case GCC_USB_HS_PHY_CFG_AHB_CLK:
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clk_enable_cbc(priv->base + USB_HS_PHY_CFG_AHB_CBCR);
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break;
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case GCC_USB2A_PHY_SLEEP_CLK:
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clk_enable_cbc(priv->base + USB_HS_PHY_CFG_AHB_CBCR);
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break;
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case GCC_ETH_PTP_CLK:
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/* SPEED_1000: freq -> 250MHz */
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clk_enable_cbc(priv->base + ETH_PTP_CBCR);
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clk_enable_gpll0(priv->base, &gpll1_vote_clk);
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clk_rcg_set_rate_mnd(priv->base, EMAC_PTP_CMD_RCGR, 3, 0, 0,
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CFG_CLK_SRC_GPLL1, 8);
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break;
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case GCC_ETH_RGMII_CLK:
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/* SPEED_1000: freq -> 250MHz */
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clk_enable_cbc(priv->base + ETH_RGMII_CBCR);
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clk_enable_gpll0(priv->base, &gpll1_vote_clk);
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clk_rcg_set_rate_mnd(priv->base, EMAC_CMD_RCGR, 3, 0, 0,
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CFG_CLK_SRC_GPLL1, 8);
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break;
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case GCC_ETH_SLAVE_AHB_CLK:
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clk_enable_cbc(priv->base + ETH_SLAVE_AHB_CBCR);
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break;
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case GCC_ETH_AXI_CLK:
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clk_enable_cbc(priv->base + ETH_AXI_CBCR);
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break;
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case GCC_BLSP1_AHB_CLK:
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clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk);
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break;
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case GCC_BLSP1_QUP0_I2C_APPS_CLK:
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clk_enable_cbc(priv->base + BLSP1_QUP0_I2C_APPS_CBCR);
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clk_rcg_set_rate(priv->base, BLSP1_QUP0_I2C_APPS_CMD_RCGR, 0,
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CFG_CLK_SRC_CXO);
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break;
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case GCC_BLSP1_QUP1_I2C_APPS_CLK:
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clk_enable_cbc(priv->base + BLSP1_QUP1_I2C_APPS_CBCR);
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clk_rcg_set_rate(priv->base, BLSP1_QUP1_I2C_APPS_CMD_RCGR, 0,
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CFG_CLK_SRC_CXO);
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break;
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case GCC_BLSP1_QUP2_I2C_APPS_CLK:
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clk_enable_cbc(priv->base + BLSP1_QUP2_I2C_APPS_CBCR);
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clk_rcg_set_rate(priv->base, BLSP1_QUP2_I2C_APPS_CMD_RCGR, 0,
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CFG_CLK_SRC_CXO);
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break;
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case GCC_BLSP1_QUP3_I2C_APPS_CLK:
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clk_enable_cbc(priv->base + BLSP1_QUP3_I2C_APPS_CBCR);
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clk_rcg_set_rate(priv->base, BLSP1_QUP3_I2C_APPS_CMD_RCGR, 0,
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CFG_CLK_SRC_CXO);
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break;
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case GCC_BLSP1_QUP4_I2C_APPS_CLK:
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clk_enable_cbc(priv->base + BLSP1_QUP4_I2C_APPS_CBCR);
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clk_rcg_set_rate(priv->base, BLSP1_QUP4_I2C_APPS_CMD_RCGR, 0,
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CFG_CLK_SRC_CXO);
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break;
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case GCC_SDCC1_AHB_CLK:
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clk_enable_cbc(priv->base + SDCC_AHB_CBCR(1));
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break;
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default:
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return 0;
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}
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return 0;
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}
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static const struct qcom_reset_map qcs404_gcc_resets[] = {
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[GCC_GENI_IR_BCR] = { 0x0F000 },
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[GCC_CDSP_RESTART] = { 0x18000 },
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[GCC_USB_HS_BCR] = { 0x41000 },
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[GCC_USB2_HS_PHY_ONLY_BCR] = { 0x41034 },
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[GCC_QUSB2_PHY_BCR] = { 0x4103c },
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[GCC_USB_HS_PHY_CFG_AHB_BCR] = { 0x0000c, 1 },
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[GCC_USB2A_PHY_BCR] = { 0x0000c, 0 },
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[GCC_USB3_PHY_BCR] = { 0x39004 },
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[GCC_USB_30_BCR] = { 0x39000 },
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[GCC_USB3PHY_PHY_BCR] = { 0x39008 },
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[GCC_PCIE_0_BCR] = { 0x3e000 },
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[GCC_PCIE_0_PHY_BCR] = { 0x3e004 },
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[GCC_PCIE_0_LINK_DOWN_BCR] = { 0x3e038 },
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[GCC_PCIEPHY_0_PHY_BCR] = { 0x3e03c },
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[GCC_PCIE_0_AXI_MASTER_STICKY_ARES] = { 0x3e040, 6},
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[GCC_PCIE_0_AHB_ARES] = { 0x3e040, 5 },
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[GCC_PCIE_0_AXI_SLAVE_ARES] = { 0x3e040, 4 },
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[GCC_PCIE_0_AXI_MASTER_ARES] = { 0x3e040, 3 },
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[GCC_PCIE_0_CORE_STICKY_ARES] = { 0x3e040, 2 },
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[GCC_PCIE_0_SLEEP_ARES] = { 0x3e040, 1 },
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[GCC_PCIE_0_PIPE_ARES] = { 0x3e040, 0 },
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[GCC_EMAC_BCR] = { 0x4e000 },
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[GCC_WDSP_RESTART] = {0x19000},
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};
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static const struct msm_clk_data qcs404_clk_gcc_data = {
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.resets = qcs404_gcc_resets,
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.num_resets = ARRAY_SIZE(qcs404_gcc_resets),
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.enable = qcs404_clk_enable,
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.set_rate = qcs404_clk_set_rate,
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};
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static const struct udevice_id gcc_qcs404_of_match[] = {
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{
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.compatible = "qcom,gcc-qcs404",
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.data = (ulong)&qcs404_clk_gcc_data
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},
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{ }
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};
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U_BOOT_DRIVER(gcc_qcs404) = {
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.name = "gcc_qcs404",
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.id = UCLASS_NOP,
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.of_match = gcc_qcs404_of_match,
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.bind = qcom_cc_bind,
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.flags = DM_FLAG_PRE_RELOC,
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};
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