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https://github.com/smaeul/u-boot.git
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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
99 lines
2.6 KiB
C
99 lines
2.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
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* Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
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*/
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#define LOG_CATEGORY UCLASS_RESET
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <log.h>
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#include <malloc.h>
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#include <reset-uclass.h>
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#include <stm32_rcc.h>
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#include <asm/io.h>
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#include <dm/device_compat.h>
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#include <linux/bitops.h>
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/* offset of register without set/clear management */
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#define RCC_MP_GCR_OFFSET 0x10C
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/* reset clear offset for STM32MP RCC */
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#define RCC_CL 0x4
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struct stm32_reset_priv {
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fdt_addr_t base;
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};
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static int stm32_reset_assert(struct reset_ctl *reset_ctl)
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{
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struct stm32_reset_priv *priv = dev_get_priv(reset_ctl->dev);
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int bank = (reset_ctl->id / (sizeof(u32) * BITS_PER_BYTE)) * 4;
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int offset = reset_ctl->id % (sizeof(u32) * BITS_PER_BYTE);
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dev_dbg(reset_ctl->dev, "reset id = %ld bank = %d offset = %d)\n",
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reset_ctl->id, bank, offset);
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if (dev_get_driver_data(reset_ctl->dev) == STM32MP1)
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if (bank != RCC_MP_GCR_OFFSET)
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/* reset assert is done in rcc set register */
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writel(BIT(offset), priv->base + bank);
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else
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clrbits_le32(priv->base + bank, BIT(offset));
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else
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setbits_le32(priv->base + bank, BIT(offset));
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return 0;
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}
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static int stm32_reset_deassert(struct reset_ctl *reset_ctl)
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{
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struct stm32_reset_priv *priv = dev_get_priv(reset_ctl->dev);
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int bank = (reset_ctl->id / (sizeof(u32) * BITS_PER_BYTE)) * 4;
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int offset = reset_ctl->id % (sizeof(u32) * BITS_PER_BYTE);
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dev_dbg(reset_ctl->dev, "reset id = %ld bank = %d offset = %d)\n",
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reset_ctl->id, bank, offset);
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if (dev_get_driver_data(reset_ctl->dev) == STM32MP1)
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if (bank != RCC_MP_GCR_OFFSET)
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/* reset deassert is done in rcc clr register */
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writel(BIT(offset), priv->base + bank + RCC_CL);
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else
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setbits_le32(priv->base + bank, BIT(offset));
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else
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clrbits_le32(priv->base + bank, BIT(offset));
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return 0;
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}
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static const struct reset_ops stm32_reset_ops = {
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.rst_assert = stm32_reset_assert,
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.rst_deassert = stm32_reset_deassert,
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};
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static int stm32_reset_probe(struct udevice *dev)
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{
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struct stm32_reset_priv *priv = dev_get_priv(dev);
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priv->base = dev_read_addr(dev);
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if (priv->base == FDT_ADDR_T_NONE) {
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/* for MFD, get address of parent */
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priv->base = dev_read_addr(dev->parent);
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if (priv->base == FDT_ADDR_T_NONE)
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return -EINVAL;
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}
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return 0;
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}
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U_BOOT_DRIVER(stm32_rcc_reset) = {
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.name = "stm32_rcc_reset",
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.id = UCLASS_RESET,
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.probe = stm32_reset_probe,
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.priv_auto = sizeof(struct stm32_reset_priv),
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.ops = &stm32_reset_ops,
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};
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