mirror of
https://github.com/smaeul/u-boot.git
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03de305ec4
As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
265 lines
6.7 KiB
C
265 lines
6.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Based on vendor support provided by AVNET Embedded
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*
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* Copyright (C) 2021 AVNET Embedded, MSC Technologies GmbH
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* Copyright 2021 General Electric Company
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* Copyright 2021 Collabora Ltd.
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*/
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#include <config.h>
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#include <cpu_func.h>
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#include <fsl_esdhc_imx.h>
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#include <hang.h>
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#include <i2c.h>
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#include <image.h>
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#include <init.h>
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#include <log.h>
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#include <mmc.h>
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#include <spl.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/ddr.h>
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#include <asm/arch/imx8mp_pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/mach-imx/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <dm/uclass.h>
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#include <dm/device.h>
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#include <linux/delay.h>
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#include <power/pmic.h>
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#include <power/rn5t567_pmic.h>
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DECLARE_GLOBAL_DATA_PTR;
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int spl_board_boot_device(enum boot_device boot_dev_spl)
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{
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return BOOT_DEVICE_BOOTROM;
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}
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void spl_dram_init(void)
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{
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ddr_init(&dram_timing);
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}
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void spl_board_init(void)
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{
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/*
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* Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does
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* not allow to change it. Should set the clock after PMIC
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* setting done. Default is 400Mhz (system_pll1_800m with div = 2)
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* set by ROM for ND VDD_SOC
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*/
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clock_enable(CCGR_GIC, 0);
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clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
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clock_enable(CCGR_GIC, 1);
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puts("Normal Boot\n");
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}
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#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE \
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| PAD_CTL_PE | PAD_CTL_FSEL2)
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#define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1)
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#define USDHC_CD_PAD_CTRL (PAD_CTL_PE | PAD_CTL_PUE | PAD_CTL_HYS \
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| PAD_CTL_DSE4)
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static const iomux_v3_cfg_t usdhc2_pads[] = {
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MX8MP_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX8MP_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX8MP_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX8MP_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX8MP_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX8MP_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX8MP_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
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MX8MP_PAD_SD2_WP__GPIO2_IO20 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
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MX8MP_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_CD_PAD_CTRL),
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};
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#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
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#define USDHC2_RESET_GPIO IMX_GPIO_NR(2, 19)
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static const iomux_v3_cfg_t usdhc3_pads[] = {
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MX8MP_PAD_NAND_WE_B__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX8MP_PAD_NAND_WP_B__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX8MP_PAD_NAND_DATA04__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX8MP_PAD_NAND_DATA05__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX8MP_PAD_NAND_DATA06__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX8MP_PAD_NAND_DATA07__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX8MP_PAD_NAND_RE_B__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX8MP_PAD_NAND_CE2_B__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX8MP_PAD_NAND_CE3_B__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX8MP_PAD_NAND_CLE__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX8MP_PAD_NAND_READY_B__USDHC3_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX8MP_PAD_NAND_CE1_B__USDHC3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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};
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static struct fsl_esdhc_cfg usdhc_cfg[] = {
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{ USDHC2_BASE_ADDR, 0, 4 },
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{ USDHC3_BASE_ADDR, 0, 8 },
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};
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int board_mmc_init(struct bd_info *bis)
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{
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int i, ret;
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/*
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* According to the board_mmc_init() the following map is done:
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* (U-Boot device node) (Physical Port)
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* mmc0 (sd) USDHC2
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* mmc1 (emmc) USDHC3
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*/
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for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
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switch (i) {
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case 0:
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init_clk_usdhc(1);
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
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imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
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ARRAY_SIZE(usdhc2_pads));
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gpio_request(USDHC2_RESET_GPIO, "usdhc2_reset");
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gpio_direction_output(USDHC2_RESET_GPIO, 0);
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udelay(500);
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gpio_direction_output(USDHC2_RESET_GPIO, 1);
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gpio_request(USDHC2_CD_GPIO, "usdhc2 cd");
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gpio_direction_input(USDHC2_CD_GPIO);
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break;
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case 1:
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init_clk_usdhc(2);
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usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
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ARRAY_SIZE(usdhc3_pads));
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break;
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default:
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printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n",
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i + 1);
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return -EINVAL;
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}
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ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
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if (ret)
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return ret;
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}
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return 0;
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}
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int board_mmc_getcd(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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int ret = 0;
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switch (cfg->esdhc_base) {
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case USDHC2_BASE_ADDR:
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ret = !gpio_get_value(USDHC2_CD_GPIO);
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break;
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case USDHC3_BASE_ADDR:
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ret = 1;
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break;
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}
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return ret;
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}
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#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
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static const iomux_v3_cfg_t wdog_pads[] = {
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MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
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};
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int board_early_init_f(void)
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{
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struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
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imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
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set_wdog_reset(wdog);
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return 0;
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}
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static const iomux_v3_cfg_t reset_out_pad[] = {
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MX8MP_PAD_SAI2_MCLK__GPIO4_IO27 | MUX_PAD_CTRL(0x19)
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};
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#define RESET_OUT_GPIO IMX_GPIO_NR(4, 27)
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static void pulse_reset_out(void)
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{
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imx_iomux_v3_setup_multiple_pads(reset_out_pad, ARRAY_SIZE(reset_out_pad));
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gpio_request(RESET_OUT_GPIO, "reset_out_gpio");
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gpio_direction_output(RESET_OUT_GPIO, 0);
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udelay(10);
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gpio_direction_output(RESET_OUT_GPIO, 1);
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}
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#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
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struct i2c_pads_info i2c_dev_pads = {
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.scl = {
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.i2c_mode = MX8MP_PAD_SAI5_RXFS__I2C6_SCL | PC,
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.gpio_mode = MX8MP_PAD_SAI5_RXFS__GPIO3_IO19 | PC,
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.gp = IMX_GPIO_NR(3, 19),
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},
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.sda = {
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.i2c_mode = MX8MP_PAD_SAI5_RXC__I2C6_SDA | PC,
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.gpio_mode = MX8MP_PAD_SAI5_RXC__GPIO3_IO20 | PC,
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.gp = IMX_GPIO_NR(3, 20),
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},
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};
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int power_init_board(void)
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{
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struct udevice *dev;
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int ret;
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ret = uclass_get_device_by_seq(UCLASS_PMIC, 0, &dev);
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if (ret) {
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printf("Error: Failed to get PMIC\n");
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return ret;
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}
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/* set VCC_DRAM (buck2) to 1.1V */
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pmic_reg_write(dev, RN5T567_DC2DAC, 0x28);
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/* set VCC_ARM (buck2) to 0.95V */
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pmic_reg_write(dev, RN5T567_DC3DAC, 0x1C);
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return 0;
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}
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int board_fit_config_name_match(const char *name)
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{
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return 0;
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}
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void board_init_f(ulong dummy)
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{
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int ret;
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arch_cpu_init();
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init_uart_clk(1);
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board_early_init_f();
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pulse_reset_out();
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timer_init();
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ret = spl_early_init();
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if (ret) {
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printf("Error: failed to initialize SPL!\n");
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hang();
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}
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preloader_console_init();
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enable_tzc380();
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power_init_board();
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spl_dram_init();
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}
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