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1a4596601f
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
160 lines
3.0 KiB
C
160 lines
3.0 KiB
C
/*
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* Copyright (C) 2008 Renesas Solutions Corp.
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* Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* PRI control register */
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#define PRPRICR5 0xFF800048 /* LMB */
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#define PRPRICR5_D 0x2a
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/* FPGA control */
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#define FPGA_NAND_CTL 0xB410020C
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#define FPGA_NAND_RST 0x0008
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#define FPGA_NAND_INIT 0x0000
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#define FPGA_NAND_RST_WAIT 10000
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/* I/O port data */
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#define PACR_D 0x0000
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#define PBCR_D 0x0000
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#define PCCR_D 0x1000
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#define PDCR_D 0x0000
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#define PECR_D 0x0410
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#define PFCR_D 0xffff
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#define PGCR_D 0x0000
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#define PHCR_D 0x5011
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#define PJCR_D 0x4400
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#define PKCR_D 0x7c00
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#define PLCR_D 0x0000
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#define PMCR_D 0x0000
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#define PNCR_D 0x0000
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#define PQCR_D 0x0000
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#define PRCR_D 0x0000
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#define PSCR_D 0x0000
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#define PTCR_D 0x0010
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#define PUCR_D 0x0fff
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#define PVCR_D 0xffff
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#define PWCR_D 0x0000
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#define PXCR_D 0x7500
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#define PYCR_D 0x0000
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#define PZCR_D 0x5540
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/* Pin Function Controler data */
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#define PSELA_D 0x1410
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#define PSELB_D 0x0140
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#define PSELC_D 0x0000
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#define PSELD_D 0x0400
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/* I/O Buffer Hi-Z data */
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#define HIZCRA_D 0x0000
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#define HIZCRB_D 0x1000
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#define HIZCRC_D 0x0000
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#define HIZCRD_D 0x0000
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/* Module select reg data */
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#define MSELCRA_D 0x0014
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#define MSELCRB_D 0x0018
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/* Module Stop reg Data */
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#define MSTPCR2_D 0xFFD9F280
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/* CPLD loader */
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extern void init_cpld(void);
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int checkboard(void)
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{
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puts("BOARD: AP325RXA\n");
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return 0;
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}
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int board_init(void)
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{
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/* Pin Function Controler Init */
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outw(PSELA_D, PSELA);
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outw(PSELB_D, PSELB);
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outw(PSELC_D, PSELC);
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outw(PSELD_D, PSELD);
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/* I/O Buffer Hi-Z Init */
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outw(HIZCRA_D, HIZCRA);
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outw(HIZCRB_D, HIZCRB);
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outw(HIZCRC_D, HIZCRC);
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outw(HIZCRD_D, HIZCRD);
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/* Module select reg Init */
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outw(MSELCRA_D, MSELCRA);
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outw(MSELCRB_D, MSELCRB);
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/* Module Stop reg Init */
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outl(MSTPCR2_D, MSTPCR2);
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/* I/O ports */
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outw(PACR_D, PACR);
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outw(PBCR_D, PBCR);
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outw(PCCR_D, PCCR);
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outw(PDCR_D, PDCR);
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outw(PECR_D, PECR);
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outw(PFCR_D, PFCR);
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outw(PGCR_D, PGCR);
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outw(PHCR_D, PHCR);
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outw(PJCR_D, PJCR);
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outw(PKCR_D, PKCR);
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outw(PLCR_D, PLCR);
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outw(PMCR_D, PMCR);
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outw(PNCR_D, PNCR);
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outw(PQCR_D, PQCR);
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outw(PRCR_D, PRCR);
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outw(PSCR_D, PSCR);
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outw(PTCR_D, PTCR);
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outw(PUCR_D, PUCR);
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outw(PVCR_D, PVCR);
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outw(PWCR_D, PWCR);
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outw(PXCR_D, PXCR);
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outw(PYCR_D, PYCR);
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outw(PZCR_D, PZCR);
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/* PRI control register Init */
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outl(PRPRICR5_D, PRPRICR5);
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/* cpld init */
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init_cpld();
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return 0;
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}
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int dram_init(void)
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{
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gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
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gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
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printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
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return 0;
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}
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void led_set_state(unsigned short value)
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{
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}
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void ide_set_reset(int idereset)
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{
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outw(FPGA_NAND_RST, FPGA_NAND_CTL); /* NAND RESET */
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udelay(FPGA_NAND_RST_WAIT);
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outw(FPGA_NAND_INIT, FPGA_NAND_CTL);
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}
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_SMC911X
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rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
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#endif
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return rc;
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}
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