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	Basically finish what the following commit started a long time ago: 488f5d8790c451fc527fe5d2ef218f2a5e40ea17 Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> For mx35pdk/woodburn: Acked-by: Stefano Babic <sbabic@denx.de>
		
			
				
	
	
		
			254 lines
		
	
	
		
			6.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			254 lines
		
	
	
		
			6.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
/*
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 * Palm LifeDrive configuration file
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 *
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 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
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 *
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 * SPDX-License-Identifier:	GPL-2.0+
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 */
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#ifndef	__CONFIG_H
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#define	__CONFIG_H
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/*
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 * High Level Board Configuration Options
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 */
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#define	CONFIG_CPU_PXA27X		1	/* Marvell PXA270 CPU */
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#define	CONFIG_PALMLD		1	/* Palm LifeDrive board */
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/* we will never enable dcache, because we have to setup MMU first */
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#define CONFIG_SYS_DCACHE_OFF
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/*
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 * Environment settings
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 */
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#define	CONFIG_ENV_OVERWRITE
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#define	CONFIG_SYS_MALLOC_LEN		(128*1024)
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#define	CONFIG_SYS_TEXT_BASE	0x0
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#define	CONFIG_BOOTCOMMAND						\
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	"if mmcinfo && fatload mmc 0 0xa0000000 uboot.script ; then "	\
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		"source 0xa0000000; "					\
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	"else "								\
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		"bootm 0x0x60000; "					\
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	"fi; "
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#define	CONFIG_BOOTARGS			"console=tty0 console=ttyS0,9600"
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#define	CONFIG_TIMESTAMP
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#define	CONFIG_BOOTDELAY		2	/* Autoboot delay */
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#define	CONFIG_CMDLINE_TAG
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#define	CONFIG_SETUP_MEMORY_TAGS
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#define	CONFIG_LZMA			/* LZMA compression support */
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/*
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 * Serial Console Configuration
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 */
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#define	CONFIG_PXA_SERIAL
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#define	CONFIG_FFUART			1
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#define CONFIG_CONS_INDEX		3
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#define	CONFIG_BAUDRATE			9600
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/*
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 * Bootloader Components Configuration
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 */
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#include <config_cmd_default.h>
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#undef	CONFIG_CMD_NET
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#undef	CONFIG_CMD_NFS
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#define	CONFIG_CMD_ENV
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#undef	CONFIG_CMD_IMLS
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#define	CONFIG_CMD_MMC
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#define	CONFIG_CMD_IDE
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#define	CONFIG_LCD
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#define	CONFIG_PXA_LCD
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/*
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 * MMC Card Configuration
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 */
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#ifdef	CONFIG_CMD_MMC
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#define	CONFIG_MMC
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#define	CONFIG_GENERIC_MMC
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#define	CONFIG_PXA_MMC_GENERIC
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#define	CONFIG_SYS_MMC_BASE		0xF0000000
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#define	CONFIG_CMD_FAT
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#define	CONFIG_CMD_EXT2
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#define	CONFIG_DOS_PARTITION
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#endif
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/*
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 * LCD
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 */
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#ifdef CONFIG_LCD
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#define	CONFIG_LQ038J7DH53
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#define	CONFIG_VIDEO_LOGO
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#define	CONFIG_CMD_BMP
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#define	CONFIG_SPLASH_SCREEN
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#define	CONFIG_SPLASH_SCREEN_ALIGN
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#define	CONFIG_VIDEO_BMP_GZIP
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#define	CONFIG_VIDEO_BMP_RLE8
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#define	CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(2 << 20)
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#endif
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/*
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 * KGDB
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 */
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#ifdef	CONFIG_CMD_KGDB
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#define	CONFIG_KGDB_BAUDRATE		230400	/* kgdb serial port speed */
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#endif
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/*
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 * HUSH Shell Configuration
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 */
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#define	CONFIG_SYS_HUSH_PARSER		1
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#define	CONFIG_SYS_LONGHELP
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#ifdef	CONFIG_SYS_HUSH_PARSER
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#define	CONFIG_SYS_PROMPT		"$ "
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#endif
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#define	CONFIG_SYS_CBSIZE		256
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#define	CONFIG_SYS_PBSIZE		\
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	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
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#define	CONFIG_SYS_MAXARGS		16
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#define	CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
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#define	CONFIG_SYS_DEVICE_NULLDEV	1
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/*
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 * Clock Configuration
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 */
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#define	CONFIG_SYS_CPUSPEED		0x210		/* 416MHz ; N=2,L=16 */
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/*
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 * DRAM Map
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 */
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#define	CONFIG_NR_DRAM_BANKS		1		/* 1 bank of DRAM */
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#define	PHYS_SDRAM_1			0xa0000000	/* SDRAM Bank #1 */
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#define	PHYS_SDRAM_1_SIZE		0x02000000	/* 32 MB */
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#define	CONFIG_SYS_DRAM_BASE		0xa0000000	/* CS0 */
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#define	CONFIG_SYS_DRAM_SIZE		0x02000000	/* 32 MB DRAM */
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#define	CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on */
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#define	CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM */
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#define	CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_DRAM_BASE
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#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
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#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
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/*
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 * NOR FLASH
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 */
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#ifdef	CONFIG_CMD_FLASH
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#define	PHYS_FLASH_1			0x00000000	/* Flash Bank #1 */
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#define	PHYS_FLASH_SIZE			0x00080000	/* 512 KB */
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#define	CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
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#define	CONFIG_SYS_FLASH_CFI
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#define	CONFIG_FLASH_CFI_DRIVER		1
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#define	CONFIG_FLASH_CFI_LEGACY
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#define	CONFIG_SYS_FLASH_LEGACY_512Kx16
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#define	CONFIG_SYS_MONITOR_BASE		0
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#define	CONFIG_SYS_MONITOR_LEN		0x40000
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#define	CONFIG_SYS_MAX_FLASH_BANKS	1
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#define	CONFIG_SYS_MAX_FLASH_SECT	256
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#define	CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
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#define	CONFIG_SYS_FLASH_ERASE_TOUT	240000
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#define	CONFIG_SYS_FLASH_WRITE_TOUT	240000
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#define	CONFIG_SYS_FLASH_LOCK_TOUT	240000
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#define	CONFIG_SYS_FLASH_UNLOCK_TOUT	240000
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#define	CONFIG_SYS_FLASH_PROTECTION
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#define	CONFIG_ENV_IS_IN_FLASH		1
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#define	CONFIG_ENV_SECT_SIZE		0x10000
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#else
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#define	CONFIG_SYS_NO_FLASH
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#define	CONFIG_ENV_IS_NOWHERE
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#endif
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#define	CONFIG_ENV_ADDR			0x40000
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#define	CONFIG_ENV_SIZE			0x4000
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/*
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 * IDE
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 */
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#ifdef	CONFIG_CMD_IDE
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#define	CONFIG_LBA48
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#undef	CONFIG_IDE_LED
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#undef	CONFIG_IDE_RESET
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#define	__io
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#define	CONFIG_SYS_IDE_MAXBUS		1
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#define	CONFIG_SYS_IDE_MAXDEVICE	1
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#define	CONFIG_SYS_ATA_BASE_ADDR	0x20000000
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#define	CONFIG_SYS_ATA_IDE0_OFFSET	0x0
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#define	CONFIG_SYS_ATA_DATA_OFFSET	0x10
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#define	CONFIG_SYS_ATA_REG_OFFSET	0x10
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#define	CONFIG_SYS_ATA_ALT_OFFSET	0x10
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#define	CONFIG_SYS_ATA_STRIDE		1
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#endif
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/*
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 * GPIO settings
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 */
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#define	CONFIG_SYS_GAFR0_L_VAL	0x00000000
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#define	CONFIG_SYS_GAFR0_U_VAL	0xa5180012
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#define	CONFIG_SYS_GAFR1_L_VAL	0x69988056
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#define	CONFIG_SYS_GAFR1_U_VAL	0xaaa580aa
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#define	CONFIG_SYS_GAFR2_L_VAL	0x6aaaaaaa
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#define	CONFIG_SYS_GAFR2_U_VAL	0x01040001
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#define	CONFIG_SYS_GAFR3_L_VAL	0x540a950c
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#define	CONFIG_SYS_GAFR3_U_VAL	0x00000009
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#define	CONFIG_SYS_GPCR0_VAL	0x00000000
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#define	CONFIG_SYS_GPCR1_VAL	0x00000000
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#define	CONFIG_SYS_GPCR2_VAL	0x00000000
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#define	CONFIG_SYS_GPCR3_VAL	0x00000000
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#define	CONFIG_SYS_GPDR0_VAL	0xc26b0000
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#define	CONFIG_SYS_GPDR1_VAL	0xfcdfaa93
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#define	CONFIG_SYS_GPDR2_VAL	0x7bbaffff
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#define	CONFIG_SYS_GPDR3_VAL	0x006ff38d
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#define	CONFIG_SYS_GPSR0_VAL	0x0d9e45ee
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#define	CONFIG_SYS_GPSR1_VAL	0x03affdae
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#define	CONFIG_SYS_GPSR2_VAL	0x07554000
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#define	CONFIG_SYS_GPSR3_VAL	0x01bc0785
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#define	CONFIG_SYS_PSSR_VAL	0x30
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/*
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 * Clock settings
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 */
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#define	CONFIG_SYS_CKEN		0x01ffffff
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#define	CONFIG_SYS_CCCR		0x02000210
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/*
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 * Memory settings
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 */
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#define	CONFIG_SYS_MSC0_VAL	0x7ff844c8
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#define	CONFIG_SYS_MSC1_VAL	0x7ff86ab4
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#define	CONFIG_SYS_MSC2_VAL	0x7ff87ff8
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#define	CONFIG_SYS_MDCNFG_VAL	0x0B880acd
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#define	CONFIG_SYS_MDREFR_VAL	0x201fa031
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#define	CONFIG_SYS_MDMRS_VAL	0x00320032
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#define	CONFIG_SYS_FLYCNFG_VAL	0x00000000
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#define	CONFIG_SYS_SXCNFG_VAL	0x40044004
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/*
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 * PCMCIA and CF Interfaces
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 */
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#define	CONFIG_SYS_MECR_VAL	0x00000003
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#define	CONFIG_SYS_MCMEM0_VAL	0x0001c391
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#define	CONFIG_SYS_MCMEM1_VAL	0x0001c391
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#define	CONFIG_SYS_MCATT0_VAL	0x0001c391
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#define	CONFIG_SYS_MCATT1_VAL	0x0001c391
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#define	CONFIG_SYS_MCIO0_VAL	0x00014611
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#define	CONFIG_SYS_MCIO1_VAL	0x0001c391
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#endif	/* __CONFIG_H */
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