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03de305ec4
As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
150 lines
3.2 KiB
C
150 lines
3.2 KiB
C
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Microsemi Corporation
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*/
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#include <config.h>
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#include <image.h>
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#include <init.h>
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#include <asm/io.h>
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#include <led.h>
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#include <miiphy.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <asm/global_data.h>
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enum {
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BOARD_TYPE_PCB110 = 0xAABBCE00,
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BOARD_TYPE_PCB111,
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BOARD_TYPE_PCB112,
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};
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int board_early_init_r(void)
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{
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/* Prepare SPI controller to be used in master mode */
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writel(0, BASE_CFG + ICPU_SW_MODE);
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clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
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ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
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ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
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/* Address of boot parameters */
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gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE;
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return 0;
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}
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static void vcoreiii_gpio_set_alternate(int gpio, int mode)
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{
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u32 mask;
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u32 val0, val1;
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void __iomem *reg0, *reg1;
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if (gpio < 32) {
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mask = BIT(gpio);
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reg0 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT(0);
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reg1 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT(1);
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} else {
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gpio -= 32;
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mask = BIT(gpio);
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reg0 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT1(0);
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reg1 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT1(1);
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}
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val0 = readl(reg0);
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val1 = readl(reg1);
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if (mode == 1) {
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writel(val0 | mask, reg0);
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writel(val1 & ~mask, reg1);
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} else if (mode == 2) {
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writel(val0 & ~mask, reg0);
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writel(val1 | mask, reg1);
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} else if (mode == 3) {
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writel(val0 | mask, reg0);
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writel(val1 | mask, reg1);
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} else {
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writel(val0 & ~mask, reg0);
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writel(val1 & ~mask, reg1);
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}
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}
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int board_phy_config(struct phy_device *phydev)
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{
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if (gd->board_type == BOARD_TYPE_PCB110 ||
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gd->board_type == BOARD_TYPE_PCB112) {
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phy_write(phydev, 0, 31, 0x10);
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phy_write(phydev, 0, 18, 0x80F0);
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while (phy_read(phydev, 0, 18) & 0x8000)
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;
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phy_write(phydev, 0, 31, 0);
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}
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if (gd->board_type == BOARD_TYPE_PCB111) {
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phy_write(phydev, 0, 31, 0x10);
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phy_write(phydev, 0, 18, 0x80A0);
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while (phy_read(phydev, 0, 18) & 0x8000)
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;
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phy_write(phydev, 0, 14, 0x800);
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phy_write(phydev, 0, 31, 0);
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}
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return 0;
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}
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void board_debug_uart_init(void)
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{
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/* too early for the pinctrl driver, so configure the UART pins here */
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vcoreiii_gpio_set_alternate(10, 1);
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vcoreiii_gpio_set_alternate(11, 1);
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}
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static void do_board_detect(void)
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{
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int i;
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u16 pval;
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/* MIIM 1 + 2 MDC/MDIO */
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for (i = 56; i < 60; i++)
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vcoreiii_gpio_set_alternate(i, 1);
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/* small delay for settling the pins */
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mdelay(30);
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if (mscc_phy_rd(0, 0x10, 0x3, &pval) == 0 &&
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((pval >> 4) & 0x3F) == 0x3c) {
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gd->board_type = BOARD_TYPE_PCB112; /* Serval2-NID */
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} else if (mscc_phy_rd(1, 0x0, 0x3, &pval) == 0 &&
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((pval >> 4) & 0x3F) == 0x3c) {
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gd->board_type = BOARD_TYPE_PCB110; /* Jr2-24 */
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} else {
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/* Fall-back */
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gd->board_type = BOARD_TYPE_PCB111; /* Jr2-48 */
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}
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}
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#if defined(CONFIG_MULTI_DTB_FIT)
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int board_fit_config_name_match(const char *name)
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{
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if (gd->board_type == BOARD_TYPE_PCB110 &&
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strcmp(name, "jr2_pcb110") == 0)
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return 0;
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if (gd->board_type == BOARD_TYPE_PCB111 &&
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strcmp(name, "jr2_pcb111") == 0)
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return 0;
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if (gd->board_type == BOARD_TYPE_PCB112 &&
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strcmp(name, "serval2_pcb112") == 0)
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return 0;
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return -1;
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}
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#endif
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#if defined(CONFIG_DTB_RESELECT)
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int embedded_dtb_select(void)
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{
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do_board_detect();
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fdtdec_setup();
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return 0;
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}
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#endif
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