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03de305ec4
As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
124 lines
3.1 KiB
C
124 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* (C) Copyright 2022 - Analog Devices, Inc.
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*
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* Written and/or maintained by Timesys Corporation
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*
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* Author: Greg Malysa <greg.malysa@timesys.com>
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*
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* Ported from Linux: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
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*/
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#ifndef CLK_ADI_CLK_H
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#define CLK_ADI_CLK_H
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#include <linux/compiler_types.h>
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#include <linux/types.h>
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#include <linux/clk-provider.h>
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#define CGU_CTL 0x00
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#define CGU_PLLCTL 0x04
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#define CGU_STAT 0x08
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#define CGU_DIV 0x0C
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#define CGU_CLKOUTSEL 0x10
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#define CGU_OSCWDCTL 0x14
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#define CGU_TSCTL 0x18
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#define CGU_TSVALUE0 0x1C
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#define CGU_TSVALUE1 0x20
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#define CGU_TSCOUNT0 0x24
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#define CGU_TSCOUNT1 0x28
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#define CGU_CCBF_DIS 0x2C
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#define CGU_CCBF_STAT 0x30
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#define CGU_SCBF_DIS 0x38
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#define CGU_SCBF_STAT 0x3C
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#define CGU_DIVEX 0x40
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#define CGU_REVID 0x48
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#define CDU_CFG0 0x00
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#define CDU_CFG1 0x04
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#define CDU_CFG2 0x08
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#define CDU_CFG3 0x0C
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#define CDU_CFG4 0x10
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#define CDU_CFG5 0x14
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#define CDU_CFG6 0x18
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#define CDU_CFG7 0x1C
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#define CDU_CFG8 0x20
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#define CDU_CFG9 0x24
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#define CDU_CFG10 0x28
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#define CDU_CFG11 0x2C
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#define CDU_CFG12 0x30
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#define CDU_CFG13 0x34
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#define CDU_CFG14 0x38
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#define PLL3_OFFSET 0x2c
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#define CDU_CLKINSEL 0x44
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#define CGU_MSEL_SHIFT 8
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#define CGU_MSEL_WIDTH 7
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#define PLL3_MSEL_SHIFT 4
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#define PLL3_MSEL_WIDTH 7
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#define CDU_MUX_SIZE 4
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#define CDU_MUX_SHIFT 1
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#define CDU_MUX_WIDTH 2
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#define CDU_EN_BIT 0
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extern const struct clk_ops adi_clk_ops;
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struct clk *sc5xx_cgu_pll(const char *name, const char *parent_name,
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void __iomem *base, u8 shift, u8 width, u32 m_offset, bool half_m);
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/**
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* All CDU clock muxes are the same size
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*/
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static inline struct clk *cdu_mux(const char *name, void __iomem *reg,
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const char * const *parents)
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{
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return clk_register_mux(NULL, name, parents, CDU_MUX_SIZE,
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CLK_SET_RATE_PARENT, reg, CDU_MUX_SHIFT, CDU_MUX_WIDTH, 0);
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}
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static inline struct clk *cgu_divider(const char *name, const char *parent,
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void __iomem *reg, u8 shift, u8 width, u8 extra_flags)
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{
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return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
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reg, shift, width, CLK_DIVIDER_MAX_AT_ZERO | extra_flags);
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}
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static inline struct clk *cdu_gate(const char *name, const char *parent,
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void __iomem *reg, u32 flags)
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{
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return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT | flags,
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reg, CDU_EN_BIT, 0, NULL);
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}
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static inline struct clk *cgu_gate(const char *name, const char *parent,
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void __iomem *reg, u8 bit)
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{
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return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, bit,
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CLK_GATE_SET_TO_DISABLE, NULL);
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}
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static inline int cdu_check_clocks(struct clk *clks[], size_t count)
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{
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size_t i;
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for (i = 0; i < count; ++i) {
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if (clks[i]) {
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if (IS_ERR(clks[i])) {
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pr_err("Clock %zu failed to register: %ld\n", i, PTR_ERR(clks[i]));
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return PTR_ERR(clks[i]);
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}
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clks[i]->id = i;
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} else {
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pr_err("ADI Clock framework: Null pointer detected on clock %zu\n", i);
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}
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}
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return 0;
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}
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#endif
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