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3e23794181
Add upower api support, this is modified from upower firmware exported package. Signed-off-by: Peng Fan <peng.fan@nxp.com>
259 lines
8.5 KiB
C
259 lines
8.5 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Copyright 2020 NXP
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*/
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enum soc_domain {
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RTD_DOMAIN = 0,
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APD_DOMAIN = 1,
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UPWR_MAIN_DOMAINS, /* RTD, AVD */
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AVD_DOMAIN = UPWR_MAIN_DOMAINS,
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UPWR_DOMAIN_COUNT, /* RTD, APD, AVD */
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PSD_DOMAIN = UPWR_DOMAIN_COUNT,
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UPWR_ALL_DOMAINS /* RTD, APD, AVD, PSD */
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};
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enum upwr_api_state {
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UPWR_API_INIT_WAIT, /* waiting for ROM firmware initialization */
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UPWR_API_INITLZED, /* ROM firmware initialized */
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UPWR_API_START_WAIT, /* waiting for start services */
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UPWR_API_READY /* ready to receive service requests */
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};
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enum upwr_sg { /* Service Groups in priority order, high to low */
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UPWR_SG_EXCEPT, /* 0 = exception */
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UPWR_SG_PWRMGMT, /* 1 = power management */
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UPWR_SG_DELAYM, /* 2 = delay measurement */
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UPWR_SG_VOLTM, /* 3 = voltage measurement */
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UPWR_SG_CURRM, /* 4 = current measurement */
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UPWR_SG_TEMPM, /* 5 = temperature measurement */
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UPWR_SG_DIAG, /* 6 = diagnostic */
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UPWR_SG_COUNT
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};
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enum upwr_xcp_f { /* Exception Functions */
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/* 0 = init msg (not a service request itself) */
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UPWR_XCP_INIT,
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/* 0 = also ping request, since its response is an init msg */
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UPWR_XCP_PING = UPWR_XCP_INIT,
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UPWR_XCP_START, /* 1 = service start: upwr_start (not a service request itself) */
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UPWR_XCP_SHUTDOWN, /* 2 = service shutdown: upwr_xcp_shutdown */
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UPWR_XCP_CONFIG, /* 3 = uPower configuration: upwr_xcp_config */
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UPWR_XCP_SW_ALARM, /* 4 = uPower software alarm: upwr_xcp_sw_alarm */
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UPWR_XCP_I2C, /* 5 = I2C access: upwr_xcp_i2c_access */
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UPWR_XCP_SPARE_6, /* 6 = spare */
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UPWR_XCP_SET_DDR_RETN, /* 7 = set/clear ddr retention */
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UPWR_XCP_SPARE_8, /* 8 = spare */
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UPWR_XCP_SPARE_9, /* 9 = spare */
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UPWR_XCP_SPARE_10, /* 10 = spare */
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UPWR_XCP_SPARE_11, /* 11 = spare */
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UPWR_XCP_SPARE_12, /* 12 = spare */
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UPWR_XCP_SPARE_13, /* 13 = spare */
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UPWR_XCP_SPARE_14, /* 14 = spare */
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UPWR_XCP_SPARE_15, /* 15 = spare */
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UPWR_XCP_F_COUNT
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};
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enum upwr_resp { /* response error codes */
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UPWR_RESP_OK = 0, /* no error */
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UPWR_RESP_SG_BUSY, /* service group is busy */
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UPWR_RESP_SHUTDOWN, /* services not up or shutting down */
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UPWR_RESP_BAD_REQ, /* invalid request */
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UPWR_RESP_BAD_STATE, /* system state doesn't allow perform the request */
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UPWR_RESP_UNINSTALLD, /* service or function not installed */
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UPWR_RESP_UNINSTALLED =
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UPWR_RESP_UNINSTALLD, /* service or function not installed (alias) */
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UPWR_RESP_RESOURCE, /* resource not available */
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UPWR_RESP_TIMEOUT, /* service timeout */
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UPWR_RESP_COUNT
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};
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#define UPWR_SRVGROUP_BITS (4)
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#define UPWR_FUNCTION_BITS (4)
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#define UPWR_PWDOMAIN_BITS (4)
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#define UPWR_HEADER_BITS (UPWR_SRVGROUP_BITS + UPWR_FUNCTION_BITS + UPWR_PWDOMAIN_BITS)
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#define UPWR_ARG_BITS (32 - UPWR_HEADER_BITS)
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#define UPWR_DUAL_OFFSET_BITS ((UPWR_ARG_BITS + 32) >> 1)
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struct upwr_msg_hdr {
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u32 domain :UPWR_PWDOMAIN_BITS; /* power domain */
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u32 srvgrp :UPWR_SRVGROUP_BITS; /* service group */
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u32 function :UPWR_FUNCTION_BITS; /* function */
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u32 arg :UPWR_ARG_BITS; /* function-specific argument */
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};
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union upwr_down_1w_msg {
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struct upwr_msg_hdr hdr;
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u32 word; /* message first word */
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};
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#define upwr_start_msg union upwr_down_1w_msg
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#define upwr_xcp_ping_msg union upwr_down_1w_msg
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#define UPWR_RESP_ERR_BITS (4)
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#define UPWR_RESP_HDR_BITS (UPWR_RESP_ERR_BITS + \
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UPWR_SRVGROUP_BITS + UPWR_FUNCTION_BITS)
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#define UPWR_RESP_RET_BITS (32 - UPWR_RESP_HDR_BITS)
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struct upwr_resp_hdr {
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u32 errcode :UPWR_RESP_ERR_BITS;
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u32 srvgrp :UPWR_SRVGROUP_BITS; /* service group */
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u32 function:UPWR_FUNCTION_BITS;
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u32 ret :UPWR_RESP_RET_BITS; /* return value, if any */
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};
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struct upwr_up_2w_msg {
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struct upwr_resp_hdr hdr;
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u32 word2; /* message second word */
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};
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#define upwr_up_max_msg struct upwr_up_2w_msg
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union upwr_2pointer_msg {
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struct upwr_msg_hdr hdr;
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struct {
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u64:UPWR_HEADER_BITS;
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u64 ptr0:UPWR_DUAL_OFFSET_BITS;
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u64 ptr1:UPWR_DUAL_OFFSET_BITS;
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} ptrs;
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};
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#define upwr_pwm_pwron_msg union upwr_2pointer_msg
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struct upwr_pointer_msg {
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struct upwr_msg_hdr hdr;
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u32 ptr; /* config struct offset */
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};
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struct upwr_i2c_access { /* structure pointed by message upwr_xcp_i2c_msg */
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u16 addr;
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s8 data_size;
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u8 subaddr_size;
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u32 subaddr;
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u32 data;
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};
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enum upwr_req_status {
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UPWR_REQ_OK, /* request succeeded */
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UPWR_REQ_ERR, /* request failed */
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UPWR_REQ_BUSY /* request execution ongoing */
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};
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#define UPWR_SOC_BITS (7)
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#define UPWR_VMINOR_BITS (4)
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#define UPWR_VFIXES_BITS (4)
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#define UPWR_VMAJOR_BITS \
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(32 - UPWR_HEADER_BITS - UPWR_SOC_BITS - UPWR_VMINOR_BITS - UPWR_VFIXES_BITS)
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union upwr_init_msg {
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struct upwr_resp_hdr hdr;
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struct {
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u32 rsv:UPWR_RESP_HDR_BITS;
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u32 soc:UPWR_SOC_BITS; /* SoC identification */
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u32 vmajor:UPWR_VMAJOR_BITS; /* firmware major version */
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u32 vminor:UPWR_VMINOR_BITS; /* firmware minor version */
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u32 vfixes:UPWR_VFIXES_BITS; /* firmware fixes version */
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} args;
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};
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#define UPWR_RAM_VMINOR_BITS (7)
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#define UPWR_RAM_VFIXES_BITS (6)
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#define UPWR_RAM_VMAJOR_BITS (32 - UPWR_HEADER_BITS - UPWR_RAM_VFIXES_BITS - UPWR_RAM_VMINOR_BITS)
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union upwr_ready_msg {
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struct upwr_resp_hdr hdr;
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struct {
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u32 rsv:UPWR_RESP_HDR_BITS;
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u32 vmajor:UPWR_RAM_VMAJOR_BITS; /* RAM fw major version */
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u32 vminor:UPWR_RAM_VMINOR_BITS; /* RAM fw minor version */
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u32 vfixes:UPWR_RAM_VFIXES_BITS; /* RAM fw fixes version */
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} args;
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};
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struct upwr_reg_access_t {
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u32 addr;
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u32 data;
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u32 mask; /* mask=0 commands read */
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};
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union upwr_xcp_union {
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struct upwr_reg_access_t reg_access;
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};
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enum { /* Power Management Functions */
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UPWR_PWM_REGCFG, /* 0 = regulator config: upwr_pwm_reg_config */
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UPWR_PWM_DEVMODE = UPWR_PWM_REGCFG, /* deprecated, for old compile */
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UPWR_PWM_VOLT, /* 1 = voltage change: upwr_pwm_chng_reg_voltage */
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UPWR_PWM_SWITCH, /* 2 = switch control: upwr_pwm_chng_switch_mem */
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UPWR_PWM_PWR_ON, /* 3 = switch/RAM/ROM power on: upwr_pwm_power_on */
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UPWR_PWM_PWR_OFF, /* 4 = switch/RAM/ROM power off: upwr_pwm_power_off */
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UPWR_PWM_RETAIN, /* 5 = retain memory array: upwr_pwm_mem_retain */
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UPWR_PWM_DOM_BIAS, /* 6 = Domain bias control: upwr_pwm_chng_dom_bias */
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UPWR_PWM_MEM_BIAS, /* 7 = Memory bias control: upwr_pwm_chng_mem_bias */
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UPWR_PWM_PMICCFG, /* 8 = PMIC configuration: upwr_pwm_pmic_config */
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UPWR_PWM_PMICMOD = UPWR_PWM_PMICCFG, /* deprecated, for old compile */
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UPWR_PWM_PES, /* 9 = Power Event Sequencer */
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UPWR_PWM_CONFIG, /* 10= apply power mode defined configuration */
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UPWR_PWM_CFGPTR, /* 11= configuration pointer */
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UPWR_PWM_DOM_PWRON, /* 12 = domain power on: upwr_pwm_dom_power_on */
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UPWR_PWM_BOOT, /* 13 = boot start: upwr_pwm_boot_start */
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UPWR_PWM_FREQ, /* 14 = domain frequency setup */
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UPWR_PWM_PARAM, /* 15 = power management parameters */
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UPWR_PWM_F_COUNT
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};
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#ifndef UPWR_PMC_SWT_WORDS
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#define UPWR_PMC_SWT_WORDS (1)
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#endif
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#ifndef UPWR_PMC_MEM_WORDS
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#define UPWR_PMC_MEM_WORDS (2)
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#endif
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#define UPWR_API_ASSERT(c) do { } while (0)
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struct upwr_code_vers {
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u32 soc_id;
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u32 vmajor;
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u32 vminor;
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u32 vfixes;
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};
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#define UPWR_MU_MSG_SIZE (2)
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#define UPWR_MU_TSR_EMPTY ((u32)((1 << UPWR_MU_MSG_SIZE) - 1))
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#ifndef UPWR_DRAM_SHARED_BASE_ADDR
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#define UPWR_DRAM_SHARED_BASE_ADDR (0x28330000)
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#endif
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#ifndef UPWR_DRAM_SHARED_SIZE
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#define UPWR_DRAM_SHARED_SIZE (2048)
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#endif
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#define UPWR_DRAM_SHARED_ENDPLUS (UPWR_DRAM_SHARED_BASE_ADDR + UPWR_DRAM_SHARED_SIZE)
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#ifndef UPWR_API_BUFFER_BASE
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#define UPWR_API_BUFFER_BASE (0x28330600)
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#endif
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#ifndef UPWR_API_BUFFER_ENDPLUS
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#define UPWR_API_BUFFER_ENDPLUS (UPWR_DRAM_SHARED_ENDPLUS - 64)
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#endif
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typedef void (*upwr_rdy_callb)(u32 vmajor, u32 vminor, u32 vfixes);
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typedef void (*upwr_callb)(enum upwr_sg sg, u32 func, enum upwr_resp errcode, int ret);
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int upwr_init(enum soc_domain domain, struct mu_type *muptr);
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int upwr_start(u32 launchopt, const upwr_rdy_callb rdycallb);
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u32 upwr_rom_version(u32 *vmajor, u32 *vminor, u32 *vfixes);
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typedef void (*UPWR_RX_CALLB_FUNC_T)(void);
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int upwr_xcp_set_ddr_retention(enum soc_domain domain, u32 enable, const upwr_callb callb);
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int upwr_pwm_power_on(const u32 swton[], const u32 memon[], upwr_callb callb);
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int upwr_xcp_i2c_access(u16 addr, s8 data_size, u8 subaddr_size, u32 subaddr,
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u32 wdata, const upwr_callb callb);
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enum upwr_req_status upwr_poll_req_status(enum upwr_sg sg, u32 *sgfptr,
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enum upwr_resp *errptr, int *retptr,
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u32 attempts);
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void upwr_txrx_isr(void);
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