mirror of
https://github.com/smaeul/u-boot.git
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724379d9af
Add support for starting timer by setting up time stamp generator registers. This is done only for EL3 i.e. mini U-Boot case. For other cases, it will be done TF-A. Add COUNTER_FREQUENCY and IOU_SWITCH_DIVISOR0 to Kconfig so that they can be tuned as required. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/fcd8b0dc4b45a11f5e753afff42f84738ac813da.1673336645.git.michal.simek@amd.com
62 lines
1.6 KiB
C
62 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2016 - 2022, Xilinx, Inc.
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* Copyright (C) 2022, Advanced Micro Devices, Inc.
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*/
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#ifndef __ASSEMBLY__
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#include <linux/bitops.h>
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#endif
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struct crlapb_regs {
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u32 reserved0[67];
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u32 cpu_r5_ctrl;
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u32 reserved;
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u32 iou_switch_ctrl; /* 0x114 */
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u32 reserved1[13];
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u32 timestamp_ref_ctrl; /* 0x14c */
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u32 reserved3[108];
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u32 rst_cpu_r5;
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u32 reserved2[17];
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u32 rst_timestamp; /* 0x348 */
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};
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struct iou_scntrs_regs {
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u32 counter_control_register; /* 0x0 */
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u32 reserved0[7];
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u32 base_frequency_id_register; /* 0x20 */
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};
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#define VERSAL_NET_CRL_APB_BASEADDR 0xEB5E0000
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#define VERSAL_NET_IOU_SCNTR_SECURE 0xEC920000
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#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT BIT(25)
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#define IOU_SWITCH_CTRL_CLKACT_BIT BIT(25)
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#define IOU_SWITCH_CTRL_DIVISOR0_SHIFT 8
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#define IOU_SCNTRS_CONTROL_EN 1
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#define crlapb_base ((struct crlapb_regs *)VERSAL_NET_CRL_APB_BASEADDR)
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#define iou_scntr_secure ((struct iou_scntrs_regs *)VERSAL_NET_IOU_SCNTR_SECURE)
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#define PMC_TAP 0xF11A0000
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#define PMC_TAP_IDCODE (PMC_TAP + 0)
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#define PMC_TAP_VERSION (PMC_TAP + 0x4)
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# define PMC_VERSION_MASK GENMASK(7, 0)
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# define PS_VERSION_MASK GENMASK(15, 8)
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# define RTL_VERSION_MASK GENMASK(23, 16)
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# define PLATFORM_MASK GENMASK(27, 24)
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# define PLATFORM_VERSION_MASK GENMASK(31, 28)
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#define PMC_TAP_USERCODE (PMC_TAP + 0x8)
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enum versal_net_platform {
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VERSAL_NET_SILICON = 0,
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VERSAL_NET_SPP = 1,
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VERSAL_NET_EMU = 2,
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VERSAL_NET_QEMU = 3,
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};
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#define VERSAL_SLCR_BASEADDR 0xF1060000
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#define VERSAL_AXI_MUX_SEL (VERSAL_SLCR_BASEADDR + 0x504)
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#define VERSAL_OSPI_LINEAR_MODE BIT(1)
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