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99d240e8fb
amba is not approved node name for simple-bus that's why use axi instead to be aligned with other xilinx boards. Node reference is not changed that's why there is no impact but also mini configuration will never gets to OS that's why nothing should be affected from OS perspective (paths in /proc/ for example). Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/1b18a69ae47bdcb1a0795af7621d13bfecfc9861.1726219714.git.michal.simek@amd.com
102 lines
2.1 KiB
Plaintext
102 lines
2.1 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Xilinx CSE NAND board DTS
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*
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* Copyright (C) 2018 Xilinx, Inc.
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*/
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/dts-v1/;
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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model = "Zynq CSE NAND Board";
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compatible = "xlnx,zynq-cse-nand", "xlnx,zynq-7000";
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aliases {
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serial0 = &dcc;
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x400000>;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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dcc: dcc {
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compatible = "arm,dcc";
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status = "disabled";
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bootph-all;
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};
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amba: axi {
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bootph-all;
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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smcc: memory-controller@e000e000 {
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#address-cells = <1>;
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#size-cells = <1>;
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clock-names = "memclk", "apb_pclk";
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clocks = <&clkc 11>, <&clkc 44>;
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compatible = "arm,pl353-smc-r2p1", "arm,primecell";
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ranges;
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reg = <0xe000e000 0x1000>;
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nand0: flash@e1000000 {
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compatible = "arm,pl353-nand-r2p1";
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reg = <0xe1000000 0x1000000>;
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};
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};
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slcr: slcr@f8000000 {
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bootph-all;
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
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reg = <0xF8000000 0x1000>;
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ranges;
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clkc: clkc@100 {
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bootph-all;
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#clock-cells = <1>;
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compatible = "xlnx,ps7-clkc";
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clock-output-names = "armpll", "ddrpll",
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"iopll", "cpu_6or4x",
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"cpu_3or2x", "cpu_2x", "cpu_1x",
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"ddr2x", "ddr3x", "dci",
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"lqspi", "smc", "pcap", "gem0",
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"gem1", "fclk0", "fclk1",
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"fclk2", "fclk3", "can0",
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"can1", "sdio0", "sdio1",
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"uart0", "uart1", "spi0",
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"spi1", "dma", "usb0_aper",
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"usb1_aper", "gem0_aper",
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"gem1_aper", "sdio0_aper",
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"sdio1_aper", "spi0_aper",
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"spi1_aper", "can0_aper",
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"can1_aper", "i2c0_aper",
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"i2c1_aper", "uart0_aper",
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"uart1_aper", "gpio_aper",
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"lqspi_aper", "smc_aper",
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"swdt", "dbg_trc", "dbg_apb";
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reg = <0x100 0x100>;
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};
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};
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scutimer: timer@f8f00600 {
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bootph-all;
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0xf8f00600 0x20>;
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clock-frequency = <333333333>;
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};
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};
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};
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&dcc {
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status = "okay";
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};
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