mirror of
https://github.com/smaeul/u-boot.git
synced 2025-10-31 03:58:17 +00:00
24a7a3c1c0
Synchronise device tree with linux v5.19-rc5. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
287 lines
8.8 KiB
C
287 lines
8.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright 2017-2018 NXP
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*/
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#ifndef __DT_BINDINGS_CLOCK_IMX8MM_H
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#define __DT_BINDINGS_CLOCK_IMX8MM_H
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#define IMX8MM_CLK_DUMMY 0
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#define IMX8MM_CLK_32K 1
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#define IMX8MM_CLK_24M 2
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#define IMX8MM_OSC_HDMI_CLK 3
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#define IMX8MM_CLK_EXT1 4
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#define IMX8MM_CLK_EXT2 5
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#define IMX8MM_CLK_EXT3 6
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#define IMX8MM_CLK_EXT4 7
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#define IMX8MM_AUDIO_PLL1_REF_SEL 8
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#define IMX8MM_AUDIO_PLL2_REF_SEL 9
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#define IMX8MM_VIDEO_PLL1_REF_SEL 10
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#define IMX8MM_DRAM_PLL_REF_SEL 11
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#define IMX8MM_GPU_PLL_REF_SEL 12
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#define IMX8MM_VPU_PLL_REF_SEL 13
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#define IMX8MM_ARM_PLL_REF_SEL 14
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#define IMX8MM_SYS_PLL1_REF_SEL 15
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#define IMX8MM_SYS_PLL2_REF_SEL 16
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#define IMX8MM_SYS_PLL3_REF_SEL 17
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#define IMX8MM_AUDIO_PLL1 18
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#define IMX8MM_AUDIO_PLL2 19
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#define IMX8MM_VIDEO_PLL1 20
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#define IMX8MM_DRAM_PLL 21
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#define IMX8MM_GPU_PLL 22
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#define IMX8MM_VPU_PLL 23
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#define IMX8MM_ARM_PLL 24
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#define IMX8MM_SYS_PLL1 25
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#define IMX8MM_SYS_PLL2 26
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#define IMX8MM_SYS_PLL3 27
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#define IMX8MM_AUDIO_PLL1_BYPASS 28
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#define IMX8MM_AUDIO_PLL2_BYPASS 29
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#define IMX8MM_VIDEO_PLL1_BYPASS 30
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#define IMX8MM_DRAM_PLL_BYPASS 31
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#define IMX8MM_GPU_PLL_BYPASS 32
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#define IMX8MM_VPU_PLL_BYPASS 33
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#define IMX8MM_ARM_PLL_BYPASS 34
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#define IMX8MM_SYS_PLL1_BYPASS 35
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#define IMX8MM_SYS_PLL2_BYPASS 36
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#define IMX8MM_SYS_PLL3_BYPASS 37
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#define IMX8MM_AUDIO_PLL1_OUT 38
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#define IMX8MM_AUDIO_PLL2_OUT 39
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#define IMX8MM_VIDEO_PLL1_OUT 40
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#define IMX8MM_DRAM_PLL_OUT 41
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#define IMX8MM_GPU_PLL_OUT 42
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#define IMX8MM_VPU_PLL_OUT 43
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#define IMX8MM_ARM_PLL_OUT 44
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#define IMX8MM_SYS_PLL1_OUT 45
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#define IMX8MM_SYS_PLL2_OUT 46
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#define IMX8MM_SYS_PLL3_OUT 47
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#define IMX8MM_SYS_PLL1_40M 48
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#define IMX8MM_SYS_PLL1_80M 49
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#define IMX8MM_SYS_PLL1_100M 50
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#define IMX8MM_SYS_PLL1_133M 51
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#define IMX8MM_SYS_PLL1_160M 52
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#define IMX8MM_SYS_PLL1_200M 53
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#define IMX8MM_SYS_PLL1_266M 54
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#define IMX8MM_SYS_PLL1_400M 55
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#define IMX8MM_SYS_PLL1_800M 56
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#define IMX8MM_SYS_PLL2_50M 57
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#define IMX8MM_SYS_PLL2_100M 58
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#define IMX8MM_SYS_PLL2_125M 59
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#define IMX8MM_SYS_PLL2_166M 60
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#define IMX8MM_SYS_PLL2_200M 61
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#define IMX8MM_SYS_PLL2_250M 62
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#define IMX8MM_SYS_PLL2_333M 63
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#define IMX8MM_SYS_PLL2_500M 64
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#define IMX8MM_SYS_PLL2_1000M 65
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/* core */
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#define IMX8MM_CLK_A53_SRC 66
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#define IMX8MM_CLK_M4_SRC 67
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#define IMX8MM_CLK_VPU_SRC 68
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#define IMX8MM_CLK_GPU3D_SRC 69
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#define IMX8MM_CLK_GPU2D_SRC 70
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#define IMX8MM_CLK_A53_CG 71
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#define IMX8MM_CLK_M4_CG 72
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#define IMX8MM_CLK_VPU_CG 73
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#define IMX8MM_CLK_GPU3D_CG 74
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#define IMX8MM_CLK_GPU2D_CG 75
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#define IMX8MM_CLK_A53_DIV 76
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#define IMX8MM_CLK_M4_DIV 77
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#define IMX8MM_CLK_VPU_DIV 78
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#define IMX8MM_CLK_GPU3D_DIV 79
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#define IMX8MM_CLK_GPU2D_DIV 80
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/* bus */
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#define IMX8MM_CLK_MAIN_AXI 81
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#define IMX8MM_CLK_ENET_AXI 82
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#define IMX8MM_CLK_NAND_USDHC_BUS 83
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#define IMX8MM_CLK_VPU_BUS 84
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#define IMX8MM_CLK_DISP_AXI 85
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#define IMX8MM_CLK_DISP_APB 86
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#define IMX8MM_CLK_DISP_RTRM 87
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#define IMX8MM_CLK_USB_BUS 88
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#define IMX8MM_CLK_GPU_AXI 89
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#define IMX8MM_CLK_GPU_AHB 90
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#define IMX8MM_CLK_NOC 91
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#define IMX8MM_CLK_NOC_APB 92
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#define IMX8MM_CLK_AHB 93
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#define IMX8MM_CLK_AUDIO_AHB 94
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#define IMX8MM_CLK_IPG_ROOT 95
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#define IMX8MM_CLK_IPG_AUDIO_ROOT 96
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#define IMX8MM_CLK_DRAM_ALT 97
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#define IMX8MM_CLK_DRAM_APB 98
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#define IMX8MM_CLK_VPU_G1 99
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#define IMX8MM_CLK_VPU_G2 100
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#define IMX8MM_CLK_DISP_DTRC 101
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#define IMX8MM_CLK_DISP_DC8000 102
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#define IMX8MM_CLK_PCIE1_CTRL 103
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#define IMX8MM_CLK_PCIE1_PHY 104
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#define IMX8MM_CLK_PCIE1_AUX 105
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#define IMX8MM_CLK_DC_PIXEL 106
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#define IMX8MM_CLK_LCDIF_PIXEL 107
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#define IMX8MM_CLK_SAI1 108
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#define IMX8MM_CLK_SAI2 109
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#define IMX8MM_CLK_SAI3 110
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#define IMX8MM_CLK_SAI4 111
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#define IMX8MM_CLK_SAI5 112
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#define IMX8MM_CLK_SAI6 113
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#define IMX8MM_CLK_SPDIF1 114
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#define IMX8MM_CLK_SPDIF2 115
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#define IMX8MM_CLK_ENET_REF 116
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#define IMX8MM_CLK_ENET_TIMER 117
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#define IMX8MM_CLK_ENET_PHY_REF 118
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#define IMX8MM_CLK_NAND 119
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#define IMX8MM_CLK_QSPI 120
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#define IMX8MM_CLK_USDHC1 121
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#define IMX8MM_CLK_USDHC2 122
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#define IMX8MM_CLK_I2C1 123
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#define IMX8MM_CLK_I2C2 124
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#define IMX8MM_CLK_I2C3 125
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#define IMX8MM_CLK_I2C4 126
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#define IMX8MM_CLK_UART1 127
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#define IMX8MM_CLK_UART2 128
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#define IMX8MM_CLK_UART3 129
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#define IMX8MM_CLK_UART4 130
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#define IMX8MM_CLK_USB_CORE_REF 131
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#define IMX8MM_CLK_USB_PHY_REF 132
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#define IMX8MM_CLK_ECSPI1 133
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#define IMX8MM_CLK_ECSPI2 134
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#define IMX8MM_CLK_PWM1 135
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#define IMX8MM_CLK_PWM2 136
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#define IMX8MM_CLK_PWM3 137
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#define IMX8MM_CLK_PWM4 138
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#define IMX8MM_CLK_GPT1 139
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#define IMX8MM_CLK_WDOG 140
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#define IMX8MM_CLK_WRCLK 141
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#define IMX8MM_CLK_DSI_CORE 142
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#define IMX8MM_CLK_DSI_PHY_REF 143
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#define IMX8MM_CLK_DSI_DBI 144
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#define IMX8MM_CLK_USDHC3 145
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#define IMX8MM_CLK_CSI1_CORE 146
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#define IMX8MM_CLK_CSI1_PHY_REF 147
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#define IMX8MM_CLK_CSI1_ESC 148
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#define IMX8MM_CLK_CSI2_CORE 149
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#define IMX8MM_CLK_CSI2_PHY_REF 150
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#define IMX8MM_CLK_CSI2_ESC 151
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#define IMX8MM_CLK_PCIE2_CTRL 152
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#define IMX8MM_CLK_PCIE2_PHY 153
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#define IMX8MM_CLK_PCIE2_AUX 154
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#define IMX8MM_CLK_ECSPI3 155
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#define IMX8MM_CLK_PDM 156
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#define IMX8MM_CLK_VPU_H1 157
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#define IMX8MM_CLK_CLKO1 158
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#define IMX8MM_CLK_ECSPI1_ROOT 159
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#define IMX8MM_CLK_ECSPI2_ROOT 160
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#define IMX8MM_CLK_ECSPI3_ROOT 161
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#define IMX8MM_CLK_ENET1_ROOT 162
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#define IMX8MM_CLK_GPT1_ROOT 163
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#define IMX8MM_CLK_I2C1_ROOT 164
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#define IMX8MM_CLK_I2C2_ROOT 165
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#define IMX8MM_CLK_I2C3_ROOT 166
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#define IMX8MM_CLK_I2C4_ROOT 167
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#define IMX8MM_CLK_OCOTP_ROOT 168
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#define IMX8MM_CLK_PCIE1_ROOT 169
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#define IMX8MM_CLK_PWM1_ROOT 170
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#define IMX8MM_CLK_PWM2_ROOT 171
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#define IMX8MM_CLK_PWM3_ROOT 172
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#define IMX8MM_CLK_PWM4_ROOT 173
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#define IMX8MM_CLK_QSPI_ROOT 174
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#define IMX8MM_CLK_NAND_ROOT 175
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#define IMX8MM_CLK_SAI1_ROOT 176
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#define IMX8MM_CLK_SAI1_IPG 177
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#define IMX8MM_CLK_SAI2_ROOT 178
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#define IMX8MM_CLK_SAI2_IPG 179
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#define IMX8MM_CLK_SAI3_ROOT 180
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#define IMX8MM_CLK_SAI3_IPG 181
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#define IMX8MM_CLK_SAI4_ROOT 182
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#define IMX8MM_CLK_SAI4_IPG 183
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#define IMX8MM_CLK_SAI5_ROOT 184
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#define IMX8MM_CLK_SAI5_IPG 185
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#define IMX8MM_CLK_SAI6_ROOT 186
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#define IMX8MM_CLK_SAI6_IPG 187
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#define IMX8MM_CLK_UART1_ROOT 188
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#define IMX8MM_CLK_UART2_ROOT 189
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#define IMX8MM_CLK_UART3_ROOT 190
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#define IMX8MM_CLK_UART4_ROOT 191
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#define IMX8MM_CLK_USB1_CTRL_ROOT 192
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#define IMX8MM_CLK_GPU3D_ROOT 193
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#define IMX8MM_CLK_USDHC1_ROOT 194
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#define IMX8MM_CLK_USDHC2_ROOT 195
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#define IMX8MM_CLK_WDOG1_ROOT 196
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#define IMX8MM_CLK_WDOG2_ROOT 197
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#define IMX8MM_CLK_WDOG3_ROOT 198
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#define IMX8MM_CLK_VPU_G1_ROOT 199
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#define IMX8MM_CLK_GPU_BUS_ROOT 200
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#define IMX8MM_CLK_VPU_H1_ROOT 201
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#define IMX8MM_CLK_VPU_G2_ROOT 202
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#define IMX8MM_CLK_PDM_ROOT 203
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#define IMX8MM_CLK_DISP_ROOT 204
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#define IMX8MM_CLK_DISP_AXI_ROOT 205
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#define IMX8MM_CLK_DISP_APB_ROOT 206
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#define IMX8MM_CLK_DISP_RTRM_ROOT 207
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#define IMX8MM_CLK_USDHC3_ROOT 208
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#define IMX8MM_CLK_TMU_ROOT 209
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#define IMX8MM_CLK_VPU_DEC_ROOT 210
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#define IMX8MM_CLK_SDMA1_ROOT 211
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#define IMX8MM_CLK_SDMA2_ROOT 212
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#define IMX8MM_CLK_SDMA3_ROOT 213
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#define IMX8MM_CLK_GPT_3M 214
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#define IMX8MM_CLK_ARM 215
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#define IMX8MM_CLK_PDM_IPG 216
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#define IMX8MM_CLK_GPU2D_ROOT 217
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#define IMX8MM_CLK_MU_ROOT 218
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#define IMX8MM_CLK_CSI1_ROOT 219
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#define IMX8MM_CLK_DRAM_CORE 220
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#define IMX8MM_CLK_DRAM_ALT_ROOT 221
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#define IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK 222
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#define IMX8MM_CLK_GPIO1_ROOT 223
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#define IMX8MM_CLK_GPIO2_ROOT 224
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#define IMX8MM_CLK_GPIO3_ROOT 225
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#define IMX8MM_CLK_GPIO4_ROOT 226
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#define IMX8MM_CLK_GPIO5_ROOT 227
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#define IMX8MM_CLK_SNVS_ROOT 228
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#define IMX8MM_CLK_GIC 229
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#define IMX8MM_SYS_PLL1_40M_CG 230
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#define IMX8MM_SYS_PLL1_80M_CG 231
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#define IMX8MM_SYS_PLL1_100M_CG 232
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#define IMX8MM_SYS_PLL1_133M_CG 233
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#define IMX8MM_SYS_PLL1_160M_CG 234
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#define IMX8MM_SYS_PLL1_200M_CG 235
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#define IMX8MM_SYS_PLL1_266M_CG 236
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#define IMX8MM_SYS_PLL1_400M_CG 237
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#define IMX8MM_SYS_PLL2_50M_CG 238
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#define IMX8MM_SYS_PLL2_100M_CG 239
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#define IMX8MM_SYS_PLL2_125M_CG 240
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#define IMX8MM_SYS_PLL2_166M_CG 241
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#define IMX8MM_SYS_PLL2_200M_CG 242
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#define IMX8MM_SYS_PLL2_250M_CG 243
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#define IMX8MM_SYS_PLL2_333M_CG 244
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#define IMX8MM_SYS_PLL2_500M_CG 245
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#define IMX8MM_CLK_M4_CORE 246
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#define IMX8MM_CLK_VPU_CORE 247
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#define IMX8MM_CLK_GPU3D_CORE 248
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#define IMX8MM_CLK_GPU2D_CORE 249
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#define IMX8MM_CLK_CLKO2 250
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#define IMX8MM_CLK_A53_CORE 251
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#define IMX8MM_CLK_CLKOUT1_SEL 252
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#define IMX8MM_CLK_CLKOUT1_DIV 253
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#define IMX8MM_CLK_CLKOUT1 254
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#define IMX8MM_CLK_CLKOUT2_SEL 255
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#define IMX8MM_CLK_CLKOUT2_DIV 256
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#define IMX8MM_CLK_CLKOUT2 257
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#define IMX8MM_CLK_END 258
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#endif
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