Apurva Nandan 44e2de0480 spi: cadence-quadspi: Fix check condition for DTR ops
buswidth and dtr fields in spi_mem_op are only valid when the
corresponding spi_mem_op phase has a non-zero length. For example,
SPI NAND core doesn't set buswidth when using SPI_MEM_OP_NO_ADDR
phase.

Fix the dtr checks in set_protocol() to ignore empty spi_mem_op
phases, as checking for dtr field in empty phase will result in
false negatives.

Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-04-26 13:36:52 +05:30
..
2020-06-11 15:14:04 +05:30
2023-01-26 20:53:20 +05:30
2022-03-30 13:02:55 -04:00
2023-01-26 20:53:20 +05:30
2022-01-19 18:11:34 +01:00
2023-01-26 20:53:20 +05:30
2023-01-26 20:53:20 +05:30
2022-06-15 11:34:38 +02:00
2023-01-26 20:53:20 +05:30
2023-01-26 20:53:20 +05:30
2023-01-26 20:53:20 +05:30
2021-06-25 20:59:45 +05:30
2023-01-26 20:53:20 +05:30
2023-01-26 20:53:20 +05:30
2022-10-16 12:23:22 +02:00
2023-03-09 13:15:00 +01:00
2021-02-23 10:45:55 -05:00