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dac3ce976a
Use the new symbol to refer to any 'SPL' build, including TPL and VPL Signed-off-by: Simon Glass <sjg@chromium.org>
130 lines
2.8 KiB
C
130 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/* (C) Copyright 2019 CompuLab, Ltd. <www.compulab.co.il> */
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#include <config.h>
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#include <i2c.h>
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#include <linux/kernel.h>
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#include <asm/arch/imx8mq_pins.h>
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#include <asm/mach-imx/gpio.h>
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#include <asm-generic/gpio.h>
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#include <asm/setup.h>
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#include <linux/delay.h>
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#ifdef CONFIG_XPL_BUILD
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#define CFG_SYS_I2C_EEPROM_ADDR_P1 0x51
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static iomux_v3_cfg_t const eeprom_pads[] = {
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IMX8MQ_PAD_GPIO1_IO13__GPIO1_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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#define EEPROM_WP_GPIO IMX_GPIO_NR(1, 13)
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static void cl_eeprom_we(int enable)
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{
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static int done;
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if (done) {
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gpio_direction_output(EEPROM_WP_GPIO, enable);
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return;
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}
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imx_iomux_v3_setup_multiple_pads(eeprom_pads, ARRAY_SIZE(eeprom_pads));
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gpio_request(EEPROM_WP_GPIO, "eeprom_wp");
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gpio_direction_output(EEPROM_WP_GPIO, enable);
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done = 1;
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}
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static int cl_eeprom_read(uint offset, uchar *buf, int len)
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{
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struct udevice *dev;
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int ret;
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ret = i2c_get_chip_for_busnum(1, CFG_SYS_I2C_EEPROM_ADDR_P1,
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CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &dev);
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if (ret) {
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printf("%s: Cannot find EEPROM: %d\n", __func__, ret);
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return ret;
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}
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return dm_i2c_read(dev, offset, buf, len);
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}
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static int cl_eeprom_write(uint offset, uchar *buf, int len)
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{
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struct udevice *dev;
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int ret;
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cl_eeprom_we(1);
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ret = i2c_get_chip_for_busnum(1, CFG_SYS_I2C_EEPROM_ADDR_P1,
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CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &dev);
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if (ret) {
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printf("%s: Cannot find EEPROM: %d\n", __func__, ret);
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return ret;
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}
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return dm_i2c_write(dev, offset, buf, len);
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}
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/* Reserved for fututre use area */
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#define BOARD_DDRINFO_OFFSET 0x40
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#define BOARD_DDR_SIZE 4
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static u32 board_ddrinfo = 0xdeadbeef;
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#define BOARD_DDRSUBIND_OFFSET 0x44
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#define BOARD_DDRSUBIND_SIZE 1
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static u8 board_ddrsubind = 0xff;
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#define BOARD_OSIZE_OFFSET 0x80
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#define BOARD_OSIZE_SIZE 4
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static u32 board_osize = 0xdeadbeef;
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#define BOARD_DDRINFO_VALID(A) ((A) != 0xdeadbeef)
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u32 cl_eeprom_get_ddrinfo(void)
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{
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if (!BOARD_DDRINFO_VALID(board_ddrinfo)) {
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if (cl_eeprom_read(BOARD_DDRINFO_OFFSET, (uchar *)&board_ddrinfo, BOARD_DDR_SIZE))
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return 0;
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}
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return board_ddrinfo;
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};
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u32 cl_eeprom_set_ddrinfo(u32 ddrinfo)
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{
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if (cl_eeprom_write(BOARD_DDRINFO_OFFSET, (uchar *)&ddrinfo, BOARD_DDR_SIZE))
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return 0;
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board_ddrinfo = ddrinfo;
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return board_ddrinfo;
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};
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u8 cl_eeprom_get_subind(void)
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{
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if (cl_eeprom_read(BOARD_DDRSUBIND_OFFSET, (uchar *)&board_ddrsubind, BOARD_DDRSUBIND_SIZE))
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return 0xff;
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return board_ddrsubind;
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};
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u8 cl_eeprom_set_subind(u8 ddrsubind)
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{
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if (cl_eeprom_write(BOARD_DDRSUBIND_OFFSET, (uchar *)&ddrsubind, BOARD_DDRSUBIND_SIZE))
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return 0xff;
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board_ddrsubind = ddrsubind;
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return board_ddrsubind;
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};
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/* override-size ifaces */
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u32 cl_eeprom_get_osize(void)
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{
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if (cl_eeprom_read(BOARD_OSIZE_OFFSET, (uchar *)&board_osize, BOARD_OSIZE_SIZE))
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return 0;
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return board_osize;
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};
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#endif
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