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Coreboot provides the CMOS layout in the tables it passes to U-Boot. Use that to build an editor for the CMOS settings. Signed-off-by: Simon Glass <sjg@chromium.org>
46 lines
1011 B
ReStructuredText
46 lines
1011 B
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0+
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cbcmos
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======
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Synopis
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-------
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::
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cbcmos check [<dev>]
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cbcmos update [<dev>]
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Description
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-----------
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This checks or updates the CMOS-RAM checksum value against the CMOS-RAM
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contents. It is used with coreboot, which provides information about where to
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find the checksum and what part of the CMOS RAM it covers.
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If `<dev>` is provided then the named real-time clock (RTC) device is used.
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Otherwise the default RTC is used.
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Example
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-------
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This shows checking and updating a checksum across bytes 38 and 39 of the
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CMOS RAM::
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=> rtc read 38 2
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00000038: 71 00 q.
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=> cbc check
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=> rtc write 38 66
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=> rtc read 38 2
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00000038: 66 00 f.
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=> cbc check
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Checksum 7100 error: calculated 6600
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=> cbc update
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Checksum 6600 written
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=> cbc check
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=>
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See also :ref:`cedit_cb_load` which shows an example that includes the
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configuration editor.
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