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https://github.com/smaeul/u-boot.git
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467a40dfe3
Secure Boot Target is added for NAND for P3041. For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In case of secure boot, this default address maps to Boot ROM. The Boot ROM code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is configured as SRAM. U-Boot binary will be located on SRAM configured at address 0xBFF00000. In the U-Boot code, TLB entries are created to map the virtual address 0xFFF00000 to physical address 0xBFF00000 of CPC configured as SRAM. Signed-off-by: Saksham Jain <saksham@freescale.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
98 lines
2.4 KiB
C
98 lines
2.4 KiB
C
/*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __FSL_SECURE_BOOT_H
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#define __FSL_SECURE_BOOT_H
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#include <asm/config_mpc85xx.h>
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#ifdef CONFIG_SECURE_BOOT
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#define CONFIG_CMD_ESBC_VALIDATE
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#define CONFIG_FSL_SEC_MON
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#define CONFIG_SHA_PROG_HW_ACCEL
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#define CONFIG_DM
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#define CONFIG_RSA
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#define CONFIG_RSA_FREESCALE_EXP
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#ifndef CONFIG_FSL_CAAM
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#define CONFIG_FSL_CAAM
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#endif
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#endif
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#ifdef CONFIG_SECURE_BOOT
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#if defined(CONFIG_FSL_CORENET)
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#define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000
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#elif defined(CONFIG_BSC9132QDS)
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#define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000
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#elif defined(CONFIG_C29XPCIE)
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#define CONFIG_SYS_PBI_FLASH_BASE 0xcc000000
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#else
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#define CONFIG_SYS_PBI_FLASH_BASE 0xce000000
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#endif
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#define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000
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#if defined(CONFIG_B4860QDS) || \
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defined(CONFIG_T4240QDS) || \
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defined(CONFIG_T2080QDS) || \
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defined(CONFIG_T2080RDB) || \
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defined(CONFIG_T1040QDS) || \
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defined(CONFIG_T104xD4QDS) || \
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defined(CONFIG_T104xRDB) || \
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defined(CONFIG_T104xD4RDB) || \
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defined(CONFIG_PPC_T1023) || \
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defined(CONFIG_PPC_T1024)
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#define CONFIG_SYS_CPC_REINIT_F
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#define CONFIG_KEY_REVOCATION
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#undef CONFIG_SYS_INIT_L3_ADDR
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#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
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#endif
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#if defined(CONFIG_RAMBOOT_PBL)
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#undef CONFIG_SYS_INIT_L3_ADDR
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#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
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#endif
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#if defined(CONFIG_C29XPCIE)
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#define CONFIG_KEY_REVOCATION
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#endif
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#if defined(CONFIG_PPC_P3041) || \
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defined(CONFIG_PPC_P4080) || \
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defined(CONFIG_PPC_P5020) || \
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defined(CONFIG_PPC_P5040) || \
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defined(CONFIG_PPC_P2041)
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#define CONFIG_FSL_TRUST_ARCH_v1
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#endif
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#if defined(CONFIG_FSL_CORENET)
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/* The key used for verification of next level images
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* is picked up from an Extension Table which has
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* been verified by the ISBC (Internal Secure boot Code)
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* in boot ROM of the SoC
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*/
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#define CONFIG_FSL_ISBC_KEY_EXT
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#endif
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#ifndef CONFIG_FIT_SIGNATURE
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/* The bootscript header address is different for B4860 because the NOR
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* mapping is different on B4 due to reduced NOR size.
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*/
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#if defined(CONFIG_B4860QDS)
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#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xecc00000
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#elif defined(CONFIG_FSL_CORENET)
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#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xe8e00000
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#elif defined(CONFIG_BSC9132QDS)
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#define CONFIG_BOOTSCRIPT_HDR_ADDR 0x88020000
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#elif defined(CONFIG_C29XPCIE)
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#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xec020000
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#else
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#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xee020000
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#endif
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#include <config_fsl_secboot.h>
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#endif
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#endif
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#endif
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