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c8f3402ad2
Add support for the MSC SM2S-IMX8PLUS SMARC Module. Tested in conjunction with the MSC SM2-MB-EP1 Mini-ITX Carrier Board. Signed-off-by: Martyn Welch <martyn.welch@collabora.com> Signed-off-by: Fabio Estevam <festevam@denx.de>
821 lines
20 KiB
Plaintext
821 lines
20 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2022 Avnet Embedded GmbH
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*/
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/dts-v1/;
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#include "imx8mp.dtsi"
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#include <dt-bindings/net/ti-dp83867.h>
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/ {
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aliases {
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rtc0 = &sys_rtc;
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rtc1 = &snvs_rtc;
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};
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chosen {
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stdout-path = &uart2;
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};
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reg_usb0_host_vbus: regulator-usb0-vbus {
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compatible = "regulator-fixed";
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regulator-name = "usb0_host_vbus";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb0_vbus>;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_usb1_host_vbus: regulator-usb1-vbus {
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compatible = "regulator-fixed";
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regulator-name = "usb1_host_vbus";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb1_vbus>;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_usdhc2_vmmc: regulator-usdhc2 {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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startup-delay-us = <100>;
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off-on-delay-us = <12000>;
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};
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reg_flexcan1_xceiver: regulator-flexcan1 {
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compatible = "regulator-fixed";
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regulator-name = "flexcan1-xceiver";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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reg_flexcan2_xceiver: regulator-flexcan2 {
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compatible = "regulator-fixed";
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regulator-name = "flexcan2-xceiver";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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lcd0_backlight: backlight-0 {
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compatible = "pwm-backlight";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lcd0_backlight>;
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pwms = <&pwm1 0 100000 0>;
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brightness-levels = <0 255>;
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num-interpolated-steps = <255>;
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default-brightness-level = <255>;
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enable-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
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status = "disabled";
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};
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lcd1_backlight: backlight-1 {
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compatible = "pwm-backlight";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lcd1_backlight>;
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pwms = <&pwm2 0 100000 0>;
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brightness-levels = <0 255>;
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num-interpolated-steps = <255>;
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default-brightness-level = <255>;
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enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
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status = "disabled";
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_leds>;
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status = "okay";
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led-sw {
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label = "sw-led";
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gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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linux,default-trigger = "heartbeat";
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};
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};
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extcon_usb0: extcon-usb0 {
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compatible = "linux,extcon-usb-gpio";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb0_extcon>;
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id-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
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};
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};
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&A53_0 {
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cpu-supply = <&vcc_arm>;
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};
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&A53_1 {
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cpu-supply = <&vcc_arm>;
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};
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&A53_2 {
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cpu-supply = <&vcc_arm>;
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};
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&A53_3 {
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cpu-supply = <&vcc_arm>;
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};
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&ecspi1 {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi1>;
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cs-gpios = <0>, <&gpio2 8 GPIO_ACTIVE_LOW>;
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};
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&ecspi2 {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi2>;
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cs-gpios = <0>, <&gpio2 9 GPIO_ACTIVE_LOW>;
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};
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&eqos {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_eqos>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy0>;
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status = "okay";
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mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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eee-broken-1000t;
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reset-gpios = <&tca6424 16 GPIO_ACTIVE_LOW>;
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reset-assert-us = <1000>;
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reset-deassert-us = <1000>;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
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};
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};
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy1>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy1: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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eee-broken-1000t;
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reset-gpios = <&tca6424 17 GPIO_ACTIVE_LOW>;
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reset-assert-us = <1000>;
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reset-deassert-us = <1000>;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
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};
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};
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};
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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clock-frequency = <400000>;
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status = "okay";
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id_eeprom: eeprom@50 {
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compatible = "atmel,24c64";
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reg = <0x50>;
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pagesize = <32>;
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};
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};
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&i2c2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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clock-frequency = <400000>;
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status = "disabled";
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};
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&i2c3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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clock-frequency = <400000>;
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status = "disabled";
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};
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&i2c4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c4>;
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clock-frequency = <400000>;
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status = "disabled";
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};
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&i2c5 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c5>;
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clock-frequency = <400000>;
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status = "disabled";
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};
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&i2c6 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c6>;
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clock-frequency = <400000>;
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status = "okay";
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tca6424: gpio@22 {
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compatible = "ti,tca6424";
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reg = <0x22>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_tca6424>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-line-names = "BOOT_SEL0#", "BOOT_SEL1#", "BOOT_SEL2#",
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"gbe0_int", "gbe1_int", "pmic_int", "rtc_int", "lvds_int",
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"PCIE_WAKE#", "cam2_rst", "cam2_pwr", "SLEEP#",
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"wifi_pd", "tpm_int", "wifi_int", "PCIE_A_RST#",
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"gbe0_rst", "gbe1_rst", "LID#", "BATLOW#", "CHARGING#",
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"CHARGER_PRSNT#";
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interrupt-parent = <&gpio1>;
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interrupts = <9 IRQ_TYPE_EDGE_RISING>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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dsi_lvds_bridge: bridge@2d {
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compatible = "ti,sn65dsi83";
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reg = <0x2d>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lvds_bridge>;
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enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
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status = "disabled";
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};
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pmic: pmic@30 {
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compatible = "ricoh,rn5t567";
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reg = <0x30>;
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interrupt-parent = <&tca6424>;
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interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
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regulators {
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DCDC1 {
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regulator-name = "VCC_SOC";
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regulator-always-on;
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regulator-min-microvolt = <950000>;
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regulator-max-microvolt = <950000>;
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};
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DCDC2 {
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regulator-name = "VCC_DRAM";
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regulator-always-on;
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regulator-min-microvolt = <1100000>;
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regulator-max-microvolt = <1100000>;
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};
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vcc_arm: DCDC3 {
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regulator-name = "VCC_ARM";
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regulator-always-on;
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regulator-min-microvolt = <950000>;
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regulator-max-microvolt = <950000>;
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};
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DCDC4 {
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regulator-name = "VCC_1V8";
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regulator-always-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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LDO1 {
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regulator-name = "VCC_LDO1_2V5";
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regulator-always-on;
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regulator-min-microvolt = <2500000>;
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regulator-max-microvolt = <2500000>;
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};
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LDO2 {
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regulator-name = "VCC_LDO2_1V8";
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regulator-always-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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LDO3 {
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regulator-name = "VCC_ETH_2V5";
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regulator-always-on;
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regulator-min-microvolt = <2500000>;
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regulator-max-microvolt = <2500000>;
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};
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LDO4 {
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regulator-name = "VCC_DDR4_2V5";
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regulator-always-on;
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regulator-min-microvolt = <2500000>;
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regulator-max-microvolt = <2500000>;
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};
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LDO5 {
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regulator-name = "VCC_LDO5_1V8";
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regulator-always-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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LDORTC1 {
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regulator-name = "VCC_SNVS_1V8";
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regulator-always-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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LDORTC2 {
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regulator-name = "VCC_SNVS_3V3";
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regulator-always-on;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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};
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sys_rtc: rtc@32 {
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compatible = "ricoh,r2221tl";
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reg = <0x32>;
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interrupt-parent = <&tca6424>;
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interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
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};
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tmp_sensor: temperature-sensor@71 {
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compatible = "ti,tmp103";
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reg = <0x71>;
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};
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};
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&flexcan1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan1>;
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xceiver-supply = <®_flexcan1_xceiver>;
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status = "disabled";
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};
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&flexcan2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan2>;
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xceiver-supply = <®_flexcan2_xceiver>;
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status = "disabled";
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};
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&flexspi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexspi0>;
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status = "okay";
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qspi_flash: flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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spi-max-frequency = <80000000>;
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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};
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};
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&pwm1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm1>;
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status = "disabled";
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};
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&pwm2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm2>;
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status = "disabled";
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};
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&pwm3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm3>;
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status = "disabled";
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};
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&pwm4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm4>;
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status = "disabled";
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};
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&snvs_pwrkey {
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status = "okay";
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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uart-has-rtscts;
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status = "okay";
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};
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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uart-has-rtscts;
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status = "okay";
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};
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&uart4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart4>;
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status = "disabled";
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};
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&usb3_phy0 {
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vbus-supply = <®_usb0_host_vbus>;
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status = "okay";
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};
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&usb3_phy1 {
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vbus-supply = <®_usb1_host_vbus>;
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status = "okay";
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};
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&usb3_0 {
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status = "okay";
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};
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&usb3_1 {
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status = "okay";
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};
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&usb_dwc3_0 {
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dr_mode = "otg";
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hnp-disable;
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srp-disable;
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adp-disable;
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extcon = <&extcon_usb0>;
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status = "okay";
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};
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&usb_dwc3_1 {
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dr_mode = "host";
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status = "okay";
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};
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&usdhc2 {
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assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
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assigned-clock-rates = <400000000>;
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
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pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
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cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
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wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
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bus-width = <4>;
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vmmc-supply = <®_usdhc2_vmmc>;
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status = "okay";
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};
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&usdhc3 {
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assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
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assigned-clock-rates = <400000000>;
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc3>;
|
|
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
|
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
|
|
bus-width = <8>;
|
|
non-removable;
|
|
status = "okay";
|
|
};
|
|
|
|
&wdog1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_wdog>;
|
|
fsl,ext-reset-output;
|
|
status = "okay";
|
|
};
|
|
|
|
&iomuxc {
|
|
pinctrl_ecspi1: ecspi1grp {
|
|
fsl,pins =
|
|
<MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x82>,
|
|
<MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x82>,
|
|
<MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x82>,
|
|
<MX8MP_IOMUXC_ECSPI1_SS0__ECSPI1_SS0 0x40000>,
|
|
<MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x40000>;
|
|
};
|
|
|
|
pinctrl_ecspi2: ecspi2grp {
|
|
fsl,pins =
|
|
<MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82>,
|
|
<MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82>,
|
|
<MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82>,
|
|
<MX8MP_IOMUXC_ECSPI2_SS0__ECSPI2_SS0 0x40000>,
|
|
<MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x40000>;
|
|
};
|
|
|
|
pinctrl_eqos: eqosgrp {
|
|
fsl,pins =
|
|
<MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3>,
|
|
<MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3>,
|
|
<MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91>,
|
|
<MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91>,
|
|
<MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91>,
|
|
<MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91>,
|
|
<MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91>,
|
|
<MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91>,
|
|
<MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f>,
|
|
<MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f>,
|
|
<MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f>,
|
|
<MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f>,
|
|
<MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f>,
|
|
<MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f>;
|
|
};
|
|
|
|
pinctrl_fec: fecgrp {
|
|
fsl,pins =
|
|
<MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3>,
|
|
<MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3>,
|
|
<MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91>,
|
|
<MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91>,
|
|
<MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91>,
|
|
<MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91>,
|
|
<MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91>,
|
|
<MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91>,
|
|
<MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f>,
|
|
<MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f>,
|
|
<MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f>,
|
|
<MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f>,
|
|
<MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f>,
|
|
<MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f>;
|
|
};
|
|
|
|
pinctrl_flexcan1: flexcan1grp {
|
|
fsl,pins =
|
|
<MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154>,
|
|
<MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154>;
|
|
};
|
|
|
|
pinctrl_flexcan2: flexcan2grp {
|
|
fsl,pins =
|
|
<MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154>,
|
|
<MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154>;
|
|
};
|
|
|
|
pinctrl_flexspi0: flexspi0grp {
|
|
fsl,pins =
|
|
<MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2>,
|
|
<MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82>,
|
|
<MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82>,
|
|
<MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82>,
|
|
<MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82>,
|
|
<MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82>,
|
|
<MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x19>;
|
|
};
|
|
|
|
pinctrl_i2c1: i2c1grp {
|
|
fsl,pins =
|
|
<MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3>,
|
|
<MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3>;
|
|
};
|
|
|
|
pinctrl_i2c2: i2c2grp {
|
|
fsl,pins =
|
|
<MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3>,
|
|
<MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3>;
|
|
};
|
|
|
|
pinctrl_i2c3: i2c3grp {
|
|
fsl,pins =
|
|
<MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3>,
|
|
<MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3>;
|
|
};
|
|
|
|
pinctrl_i2c4: i2c4grp {
|
|
fsl,pins =
|
|
<MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3>,
|
|
<MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3>;
|
|
};
|
|
|
|
pinctrl_i2c5: i2c5grp {
|
|
fsl,pins =
|
|
<MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c3>,
|
|
<MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c3>;
|
|
};
|
|
|
|
pinctrl_i2c6: i2c6grp {
|
|
fsl,pins =
|
|
<MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001c3>,
|
|
<MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c3>;
|
|
};
|
|
|
|
pinctrl_lcd0_backlight: lcd0-backlightgrp {
|
|
fsl,pins =
|
|
<MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x41>;
|
|
};
|
|
|
|
pinctrl_lcd1_backlight: lcd1-backlightgrp {
|
|
fsl,pins =
|
|
<MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x41>;
|
|
};
|
|
|
|
pinctrl_leds: ledsgrp {
|
|
fsl,pins =
|
|
<MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x19>;
|
|
};
|
|
|
|
pinctrl_lvds_bridge: lvds-bridgegrp {
|
|
fsl,pins =
|
|
<MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x41>;
|
|
};
|
|
|
|
pinctrl_pwm1: pwm1grp {
|
|
fsl,pins =
|
|
<MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x116>;
|
|
};
|
|
|
|
pinctrl_pwm2: pwm2grp {
|
|
fsl,pins =
|
|
<MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x116>;
|
|
};
|
|
|
|
pinctrl_pwm3: pwm3grp {
|
|
fsl,pins =
|
|
<MX8MP_IOMUXC_GPIO1_IO10__PWM3_OUT 0x116>;
|
|
};
|
|
|
|
pinctrl_pwm4: pwm4grp {
|
|
fsl,pins =
|
|
<MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT 0x116>;
|
|
};
|
|
|
|
pinctrl_tca6424: tca6424grp {
|
|
fsl,pins =
|
|
<MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x41>;
|
|
};
|
|
|
|
pinctrl_uart1: uart1grp {
|
|
fsl,pins =
|
|
<MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x49>,
|
|
<MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x49>;
|
|
};
|
|
|
|
pinctrl_uart2: uart2grp {
|
|
fsl,pins =
|
|
<MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x1c4>,
|
|
<MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x1c4>,
|
|
<MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49>,
|
|
<MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49>;
|
|
};
|
|
|
|
pinctrl_uart3: uart3grp {
|
|
fsl,pins =
|
|
<MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x1c4>,
|
|
<MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x1c4>,
|
|
<MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x49>,
|
|
<MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x49>;
|
|
};
|
|
|
|
pinctrl_uart4: uart4grp {
|
|
fsl,pins =
|
|
<MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49>,
|
|
<MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49>;
|
|
};
|
|
|
|
pinctrl_usb0_extcon: usb0-extcongrp {
|
|
fsl,pins =
|
|
<MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x19>;
|
|
};
|
|
|
|
pinctrl_usb0_vbus: usb0-vbusgrp {
|
|
fsl,pins =
|
|
<MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x19>;
|
|
};
|
|
|
|
pinctrl_usb1_vbus: usb1-vbusgrp {
|
|
fsl,pins =
|
|
<MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x19>;
|
|
};
|
|
|
|
pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
|
|
fsl,pins =
|
|
<MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4>,
|
|
<MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x1c4>;
|
|
};
|
|
|
|
pinctrl_usdhc2: usdhc2grp {
|
|
fsl,pins =
|
|
<MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190>,
|
|
<MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0>,
|
|
<MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0>,
|
|
<MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0>,
|
|
<MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0>,
|
|
<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0>,
|
|
<MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1>;
|
|
};
|
|
|
|
pinctrl_usdhc2_vmmc: usdhc2-vmmcgrp {
|
|
fsl,pins =
|
|
<MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41>;
|
|
};
|
|
|
|
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
|
|
fsl,pins =
|
|
<MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>,
|
|
<MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>,
|
|
<MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>,
|
|
<MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>,
|
|
<MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>,
|
|
<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>,
|
|
<MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1>;
|
|
};
|
|
|
|
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
|
|
fsl,pins =
|
|
<MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196>,
|
|
<MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6>,
|
|
<MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6>,
|
|
<MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6>,
|
|
<MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6>,
|
|
<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6>,
|
|
<MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1>;
|
|
};
|
|
|
|
pinctrl_usdhc3: usdhc3grp {
|
|
fsl,pins =
|
|
<MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190>,
|
|
<MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0>,
|
|
<MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0>,
|
|
<MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0>,
|
|
<MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0>,
|
|
<MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0>,
|
|
<MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0>,
|
|
<MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0>,
|
|
<MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0>,
|
|
<MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0>,
|
|
<MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190>;
|
|
};
|
|
|
|
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
|
|
fsl,pins =
|
|
<MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>,
|
|
<MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>,
|
|
<MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>,
|
|
<MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>,
|
|
<MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>,
|
|
<MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>,
|
|
<MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>,
|
|
<MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>,
|
|
<MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>,
|
|
<MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>,
|
|
<MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194>;
|
|
};
|
|
|
|
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
|
|
fsl,pins =
|
|
<MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196>,
|
|
<MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6>,
|
|
<MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6>,
|
|
<MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6>,
|
|
<MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6>,
|
|
<MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6>,
|
|
<MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6>,
|
|
<MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6>,
|
|
<MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6>,
|
|
<MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6>,
|
|
<MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196>;
|
|
};
|
|
|
|
pinctrl_wdog: wdoggrp {
|
|
fsl,pins =
|
|
<MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6>;
|
|
};
|
|
};
|