Armando Visconti 491739bb74 designware_i2c: Added s/w generation of stop bit
In the newer versions of designware i2c IP there is the possibility
of configuring it with IC_EMPTYFIFO_HOLD_MASTER_EN=1, which basically
requires the s/w to generate the stop bit condition directly, as
the h/w will not automatically generate it when TX_FIFO is empty.

To avoid generation of an extra 0x0 byte sent as data, the
IC_STOP command must be sent along with the last IC_CMD.

This patch always writes bit[9] of ic_data_cmd even in the
older versions, assuming that it is a noop there.

Signed-off-by: Armando Visconti <armando.visconti@st.com>
2012-12-11 13:17:32 -07:00
..
2012-10-25 12:06:21 -07:00
2011-10-03 11:50:09 +02:00
2011-04-27 19:38:09 +02:00
2009-10-30 15:10:58 +01:00