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09bfd962bd
The read-only-write-enable bit is set by default and must be cleared to prevent overwriting read-only registers. This should be done immediately after resetting the PCI Express controller. Reviewed-by: Hamish Martin <hamish.martin@alliedtelesis.co.nz> Signed-off-by: Tony O'Brien <tony.obrien@alliedtelesis.co.nz> [York S: Move SYS_FSL_ERRATUM_A007815 to Kconfig] Reviewed-by: York Sun <york.sun@nxp.com>
348 lines
10 KiB
C
348 lines
10 KiB
C
/*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <linux/compiler.h>
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#include <fsl_errata.h>
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#include <asm/processor.h>
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#include <fsl_usb.h>
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#include "fsl_corenet_serdes.h"
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#ifdef CONFIG_SYS_FSL_ERRATUM_A004849
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/*
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* This work-around is implemented in PBI, so just check to see if the
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* work-around was actually applied. To do this, we check for specific data
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* at specific addresses in DCSR.
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*
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* Array offsets[] contains a list of offsets within DCSR. According to the
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* erratum document, the value at each offset should be 2.
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*/
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static void check_erratum_a4849(uint32_t svr)
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{
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void __iomem *dcsr = (void *)CONFIG_SYS_DCSRBAR + 0xb0000;
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unsigned int i;
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#if defined(CONFIG_ARCH_P2041) || defined(CONFIG_ARCH_P3041)
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static const uint8_t offsets[] = {
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0x50, 0x54, 0x58, 0x90, 0x94, 0x98
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};
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#endif
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#ifdef CONFIG_ARCH_P4080
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static const uint8_t offsets[] = {
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0x60, 0x64, 0x68, 0x6c, 0xa0, 0xa4, 0xa8, 0xac
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};
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#endif
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uint32_t x108; /* The value that should be at offset 0x108 */
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for (i = 0; i < ARRAY_SIZE(offsets); i++) {
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if (in_be32(dcsr + offsets[i]) != 2) {
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printf("Work-around for Erratum A004849 is not enabled\n");
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return;
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}
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}
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#if defined(CONFIG_ARCH_P2041) || defined(CONFIG_ARCH_P3041)
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x108 = 0x12;
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#endif
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#ifdef CONFIG_ARCH_P4080
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/*
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* For P4080, the erratum document says that the value at offset 0x108
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* should be 0x12 on rev2, or 0x1c on rev3.
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*/
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if (SVR_MAJ(svr) == 2)
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x108 = 0x12;
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if (SVR_MAJ(svr) == 3)
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x108 = 0x1c;
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#endif
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if (in_be32(dcsr + 0x108) != x108) {
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printf("Work-around for Erratum A004849 is not enabled\n");
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return;
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}
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/* Everything matches, so the erratum work-around was applied */
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printf("Work-around for Erratum A004849 enabled\n");
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}
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A004580
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/*
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* This work-around is implemented in PBI, so just check to see if the
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* work-around was actually applied. To do this, we check for specific data
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* at specific addresses in the SerDes register block.
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*
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* The work-around says that for each SerDes lane, write BnTTLCRy0 =
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* 0x1B00_0001, Register 2 = 0x0088_0000, and Register 3 = 0x4000_0000.
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*/
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static void check_erratum_a4580(uint32_t svr)
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{
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const serdes_corenet_t __iomem *srds_regs =
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(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
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unsigned int lane;
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for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
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if (serdes_lane_enabled(lane)) {
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const struct serdes_lane __iomem *srds_lane =
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&srds_regs->lane[serdes_get_lane_idx(lane)];
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/*
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* Verify that the values we were supposed to write in
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* the PBI are actually there. Also, the lower 15
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* bits of res4[3] should be the same as the upper 15
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* bits of res4[1].
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*/
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if ((in_be32(&srds_lane->ttlcr0) != 0x1b000001) ||
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(in_be32(&srds_lane->res4[1]) != 0x880000) ||
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(in_be32(&srds_lane->res4[3]) != 0x40000044)) {
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printf("Work-around for Erratum A004580 is "
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"not enabled\n");
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return;
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}
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}
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}
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/* Everything matches, so the erratum work-around was applied */
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printf("Work-around for Erratum A004580 enabled\n");
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}
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
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/*
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* This workaround can be implemented in PBI, or by u-boot.
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*/
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static void check_erratum_a007212(void)
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{
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u32 __iomem *plldgdcr = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
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if (in_be32(plldgdcr) & 0x1fe) {
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/* check if PLL ratio is set by workaround */
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puts("Work-around for Erratum A007212 enabled\n");
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}
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}
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#endif
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static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
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extern int enable_cpu_a011_workaround;
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#endif
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__maybe_unused u32 svr = get_svr();
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#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_SYS_FSL_ERRATUM_SATA_A001)
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if (IS_SVR_REV(svr, 1, 0)) {
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switch (SVR_SOC_VER(svr)) {
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case SVR_P1013:
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case SVR_P1022:
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puts("Work-around for Erratum SATA A001 enabled\n");
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}
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}
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#endif
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#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8)
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puts("Work-around for Erratum SERDES8 enabled\n");
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#endif
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#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9)
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puts("Work-around for Erratum SERDES9 enabled\n");
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#endif
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#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES_A005)
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puts("Work-around for Erratum SERDES-A005 enabled\n");
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#endif
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#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
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if (SVR_MAJ(svr) < 3)
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puts("Work-around for Erratum CPU22 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
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/*
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* NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
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* also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
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* The SVR has been checked by cpu_init_r().
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*/
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if (enable_cpu_a011_workaround)
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puts("Work-around for Erratum CPU-A011 enabled\n");
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#endif
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#if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999)
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puts("Work-around for Erratum CPU-A003999 enabled\n");
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#endif
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#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_A003474)
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puts("Work-around for Erratum DDR-A003474 enabled\n");
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#endif
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#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
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puts("Work-around for DDR MSYNC_IN Erratum enabled\n");
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#endif
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#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC111)
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puts("Work-around for Erratum ESDHC111 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A004468
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puts("Work-around for Erratum A004468 enabled\n");
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#endif
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#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC135)
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puts("Work-around for Erratum ESDHC135 enabled\n");
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#endif
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#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC13)
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if (SVR_MAJ(svr) < 3)
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puts("Work-around for Erratum ESDHC13 enabled\n");
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#endif
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#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC_A001)
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puts("Work-around for Erratum ESDHC-A001 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
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puts("Work-around for Erratum CPC-A002 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
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puts("Work-around for Erratum CPC-A003 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_ELBC_A001
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puts("Work-around for Erratum ELBC-A001 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
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puts("Work-around for Erratum DDR-A003 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
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puts("Work-around for Erratum DDR115 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
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puts("Work-around for Erratum DDR111 enabled\n");
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puts("Work-around for Erratum DDR134 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769
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puts("Work-around for Erratum IFC-A002769 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
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puts("Work-around for Erratum P1010-A003549 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
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puts("Work-around for Erratum IFC A-003399 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
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if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
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puts("Work-around for Erratum NMG DDR120 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
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puts("Work-around for Erratum NMG_LBC103 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
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if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
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puts("Work-around for Erratum NMG ETSEC129 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A004508
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puts("Work-around for Erratum A004508 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
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puts("Work-around for Erratum A004510 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
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puts("Work-around for Erratum SRIO-A004034 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
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puts("Work-around for Erratum A004934 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A005871
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if (IS_SVR_REV(svr, 1, 0))
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puts("Work-around for Erratum A005871 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A006475
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if (SVR_MAJ(get_svr()) == 1)
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puts("Work-around for Erratum A006475 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A006384
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if (SVR_MAJ(get_svr()) == 1)
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puts("Work-around for Erratum A006384 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A004849
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/* This work-around is implemented in PBI, so just check for it */
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check_erratum_a4849(svr);
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A004580
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/* This work-around is implemented in PBI, so just check for it */
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check_erratum_a4580(svr);
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#endif
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#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
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puts("Work-around for Erratum PCIe-A003 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_USB14
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puts("Work-around for Erratum USB14 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
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if (has_erratum_a007186())
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puts("Work-around for Erratum A007186 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A006593
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puts("Work-around for Erratum A006593 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A006379
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if (has_erratum_a006379())
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puts("Work-around for Erratum A006379 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
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if (IS_SVR_REV(svr, 1, 0))
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puts("Work-around for Erratum A003571 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
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puts("Work-around for Erratum A-005812 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A005125
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puts("Work-around for Erratum A005125 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A007075
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if (has_erratum_a007075())
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puts("Work-around for Erratum A007075 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A007798
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if (has_erratum_a007798())
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puts("Work-around for Erratum A007798 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A004477
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if (has_erratum_a004477())
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puts("Work-around for Erratum A004477 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
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if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||
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(SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
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puts("Work-around for Erratum I2C-A004447 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
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if (has_erratum_a006261())
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puts("Work-around for Erratum A006261 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
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check_erratum_a007212();
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A005434
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puts("Work-around for Erratum A-005434 enabled\n");
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#endif
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#if defined(CONFIG_SYS_FSL_ERRATUM_A008044) && \
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defined(CONFIG_A008044_WORKAROUND)
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if (IS_SVR_REV(svr, 1, 0))
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puts("Work-around for Erratum A-008044 enabled\n");
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#endif
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#if defined(CONFIG_SYS_FSL_B4860QDS_XFI_ERR) && \
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(defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS))
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puts("Work-around for Erratum XFI on B4860QDS enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A009663
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puts("Work-around for Erratum A009663 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A007907
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puts("Work-around for Erratum A007907 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A007815
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puts("Work-around for Erratum A007815 enabled\n");
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#endif
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return 0;
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}
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U_BOOT_CMD(
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errata, 1, 0, do_errata,
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"Report errata workarounds",
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""
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);
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