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	Add basic support for J721S2 SoC definition Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Hari Nagalla <hnagalla@ti.com>
		
			
				
	
	
		
			47 lines
		
	
	
		
			1.3 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			47 lines
		
	
	
		
			1.3 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /* SPDX-License-Identifier: GPL-2.0+ */
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| /*
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|  * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
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|  *	David Huang <d-huang@ti.com>
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|  */
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| #ifndef _ASM_ARCH_J721S2_SPL_H_
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| #define _ASM_ARCH_J721S2_SPL_H_
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| 
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| /* With BootMode B = 0 */
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| #include <linux/bitops.h>
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| #define BOOT_DEVICE_HYPERFLASH		0x00
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| #define BOOT_DEVICE_OSPI		0x01
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| #define BOOT_DEVICE_QSPI		0x02
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| #define BOOT_DEVICE_SPI			0x03
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| #define BOOT_DEVICE_ETHERNET		0x04
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| #define BOOT_DEVICE_I2C			0x06
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| #define BOOT_DEVICE_UART		0x07
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| #define BOOT_DEVICE_NOR			BOOT_DEVICE_HYPERFLASH
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| 
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| /* With BootMode B = 1 */
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| #define BOOT_DEVICE_MMC2		0x10
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| #define BOOT_DEVICE_MMC1		0x11
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| #define BOOT_DEVICE_DFU			0x12
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| #define BOOT_DEVICE_UFS			0x13
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| #define BOOT_DEVIE_GPMC			0x14
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| #define BOOT_DEVICE_PCIE		0x15
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| #define BOOT_DEVICE_XSPI		0x16
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| #define BOOT_DEVICE_RAM			0x17
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| #define BOOT_DEVICE_MMC2_2		0xFF /* Invalid value */
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| 
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| /* Backup boot modes with MCU Only = 0 */
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| #define BACKUP_BOOT_DEVICE_RAM		0x0
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| #define BACKUP_BOOT_DEVICE_USB		0x1
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| #define BACKUP_BOOT_DEVICE_UART		0x3
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| #define BACKUP_BOOT_DEVICE_ETHERNET	0x4
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| #define BACKUP_BOOT_DEVICE_MMC2		0x5
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| #define BACKUP_BOOT_DEVICE_SPI		0x6
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| #define BACKUP_BOOT_DEVICE_I2C		0x7
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| 
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| #define BOOT_MODE_B_SHIFT		4
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| #define BOOT_MODE_B_MASK		BIT(4)
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| 
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| #define K3_PRIMARY_BOOTMODE		0x0
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| #define K3_BACKUP_BOOTMODE		0x1
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| 
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| #endif
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