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https://github.com/smaeul/u-boot.git
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81b56a55c2
The Priv ISA states: "In systems without U-mode, the mcounteren register should not exist." Check U-Mode is present in MISA before writing to counteren, otherwise we endup with Illegal Instruction exception on systems without U-Mode. Also make checking MISA default for M-Mode. Signed-off-by: Nikita Shubin <n.shubin@yadro.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
175 lines
3.7 KiB
C
175 lines
3.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
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*/
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#include <common.h>
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#include <cpu.h>
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#include <dm.h>
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#include <dm/lists.h>
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#include <event.h>
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#include <init.h>
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#include <log.h>
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#include <asm/encoding.h>
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#include <asm/system.h>
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#include <dm/uclass-internal.h>
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#include <linux/bitops.h>
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/*
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* The variables here must be stored in the data section since they are used
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* before the bss section is available.
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*/
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#if !CONFIG_IS_ENABLED(XIP)
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u32 hart_lottery __section(".data") = 0;
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#ifdef CONFIG_AVAILABLE_HARTS
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/*
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* The main hart running U-Boot has acquired available_harts_lock until it has
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* finished initialization of global data.
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*/
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u32 available_harts_lock = 1;
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#endif
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#endif
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static inline bool supports_extension(char ext)
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{
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#if CONFIG_IS_ENABLED(RISCV_MMODE)
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return csr_read(CSR_MISA) & (1 << (ext - 'a'));
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#elif CONFIG_CPU
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struct udevice *dev;
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char desc[32];
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int i;
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uclass_find_first_device(UCLASS_CPU, &dev);
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if (!dev) {
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debug("unable to find the RISC-V cpu device\n");
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return false;
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}
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if (!cpu_get_desc(dev, desc, sizeof(desc))) {
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/*
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* skip the first 4 characters (rv32|rv64) and
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* check until underscore
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*/
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for (i = 4; i < sizeof(desc); i++) {
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if (desc[i] == '_' || desc[i] == '\0')
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break;
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if (desc[i] == ext)
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return true;
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}
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}
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return false;
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#else /* !CONFIG_CPU */
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#warning "There is no way to determine the available extensions in S-mode."
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#warning "Please convert your board to use the RISC-V CPU driver."
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return false;
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#endif /* CONFIG_CPU */
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}
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static int riscv_cpu_probe(void)
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{
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#ifdef CONFIG_CPU
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int ret;
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/* probe cpus so that RISC-V timer can be bound */
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ret = cpu_probe_all();
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if (ret)
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return log_msg_ret("RISC-V cpus probe failed\n", ret);
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#endif
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return 0;
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}
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/*
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* This is called on secondary harts just after the IPI is init'd. Currently
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* there's nothing to do, since we just need to clear any existing IPIs, and
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* that is handled by the sending of an ipi itself.
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*/
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#if CONFIG_IS_ENABLED(SMP)
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static void dummy_pending_ipi_clear(ulong hart, ulong arg0, ulong arg1)
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{
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}
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#endif
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int riscv_cpu_setup(void *ctx, struct event *event)
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{
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int ret;
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ret = riscv_cpu_probe();
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if (ret)
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return ret;
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/* Enable FPU */
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if (supports_extension('d') || supports_extension('f')) {
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csr_set(MODE_PREFIX(status), MSTATUS_FS);
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csr_write(CSR_FCSR, 0);
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}
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if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
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/*
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* Enable perf counters for cycle, time,
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* and instret counters only
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*/
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if (supports_extension('u')) {
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#ifdef CONFIG_RISCV_PRIV_1_9
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csr_write(CSR_MSCOUNTEREN, GENMASK(2, 0));
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csr_write(CSR_MUCOUNTEREN, GENMASK(2, 0));
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#else
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csr_write(CSR_MCOUNTEREN, GENMASK(2, 0));
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#endif
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}
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/* Disable paging */
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if (supports_extension('s'))
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#ifdef CONFIG_RISCV_PRIV_1_9
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csr_read_clear(CSR_MSTATUS, SR_VM);
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#else
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csr_write(CSR_SATP, 0);
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#endif
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}
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#if CONFIG_IS_ENABLED(SMP)
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ret = riscv_init_ipi();
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if (ret)
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return ret;
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/*
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* Clear all pending IPIs on secondary harts. We don't do anything on
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* the boot hart, since we never send an IPI to ourselves, and no
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* interrupts are enabled
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*/
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ret = smp_call_function((ulong)dummy_pending_ipi_clear, 0, 0, 0);
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if (ret)
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return ret;
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#endif
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return 0;
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}
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EVENT_SPY(EVT_DM_POST_INIT, riscv_cpu_setup);
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int arch_early_init_r(void)
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{
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int ret;
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ret = riscv_cpu_probe();
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if (ret)
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return ret;
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if (IS_ENABLED(CONFIG_SYSRESET_SBI))
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device_bind_driver(gd->dm_root, "sbi-sysreset",
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"sbi-sysreset", NULL);
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return 0;
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}
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/**
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* harts_early_init() - A callback function called by start.S to configure
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* feature settings of each hart.
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*
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* In a multi-core system, memory access shall be careful here, it shall
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* take care of race conditions.
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*/
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__weak void harts_early_init(void)
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{
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}
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