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f29eaadeb5
This patch adds the dtsi/dts files needed to support the Marvell Octeon TX2 CN913x DB. This is only the base port with not all interfaces supported fully. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
55 lines
1000 B
Plaintext
55 lines
1000 B
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018-2021 Marvell International Ltd.
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*/
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#include "cn9130-db-A.dts"
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#include "cn9131-db.dtsi"
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/ {
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model = "Marvell CN9131 development board (CP NOR) setup(A)";
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compatible = "marvell,cn9131-db", "marvell,armada-ap806-quad",
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"marvell,armada-ap806";
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};
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&cp1_comphy {
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/* Serdes Configuration:
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* Lane 0: PCIe0 (x2)
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* Lane 1: PCIe0 (x2)
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* Lane 2: unconnected
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* Lane 3: USB1
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* Lane 4: SFP (port 0)
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* Lane 5: SATA1
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*/
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phy0 {
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phy-type = <COMPHY_TYPE_PEX0>;
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};
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phy1 {
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phy-type = <COMPHY_TYPE_PEX0>;
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};
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phy2 {
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phy-type = <COMPHY_TYPE_UNCONNECTED>;
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};
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phy3 {
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phy-type = <COMPHY_TYPE_USB3_HOST1>;
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};
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phy4 {
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phy-type = <COMPHY_TYPE_SFI0>;
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phy-speed = <COMPHY_SPEED_10_3125G>;
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};
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phy5 {
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phy-type = <COMPHY_TYPE_SATA1>;
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};
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};
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&cp1_ethernet {
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status = "okay";
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};
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/* CON50 */
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&cp1_eth0 {
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status = "okay";
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phy-mode = "sfi"; /* lane-4 */
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marvell,sfp-tx-disable-gpio = <&cp1_gpio0 9 GPIO_ACTIVE_HIGH>;
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};
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