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b8ea3810aa
host->quirks field is only used internally in exynos_dw_mmc.c driver. To avoid cluttering the scope of struct dwmci_host, move quirks field into Exynos driver's chip data, where it can be statically defined. No functional change. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
342 lines
9.7 KiB
C
342 lines
9.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2012 SAMSUNG Electronics
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* Jaehoon Chung <jh80.chung@samsung.com>
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*/
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#ifndef __DWMMC_HW_H
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#define __DWMMC_HW_H
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#include <asm/cache.h>
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#include <asm/io.h>
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#include <mmc.h>
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#include <linux/bitops.h>
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#define DWMCI_CTRL 0x000
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#define DWMCI_PWREN 0x004
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#define DWMCI_CLKDIV 0x008
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#define DWMCI_CLKSRC 0x00c
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#define DWMCI_CLKENA 0x010
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#define DWMCI_TMOUT 0x014
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#define DWMCI_CTYPE 0x018
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#define DWMCI_BLKSIZ 0x01c
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#define DWMCI_BYTCNT 0x020
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#define DWMCI_INTMASK 0x024
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#define DWMCI_CMDARG 0x028
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#define DWMCI_CMD 0x02c
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#define DWMCI_RESP0 0x030
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#define DWMCI_RESP1 0x034
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#define DWMCI_RESP2 0x038
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#define DWMCI_RESP3 0x03c
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#define DWMCI_MINTSTS 0x040
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#define DWMCI_RINTSTS 0x044
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#define DWMCI_STATUS 0x048
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#define DWMCI_FIFOTH 0x04c
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#define DWMCI_CDETECT 0x050
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#define DWMCI_WRTPRT 0x054
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#define DWMCI_GPIO 0x058
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#define DWMCI_TCMCNT 0x05c
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#define DWMCI_TBBCNT 0x060
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#define DWMCI_DEBNCE 0x064
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#define DWMCI_USRID 0x068
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#define DWMCI_VERID 0x06c
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#define DWMCI_HCON 0x070
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#define DWMCI_UHS_REG 0x074
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#define DWMCI_BMOD 0x080
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#define DWMCI_PLDMND 0x084
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#define DWMCI_DATA 0x200
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/* Registers to support IDMAC 32-bit address mode */
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#define DWMCI_DBADDR 0x088
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#define DWMCI_IDSTS 0x08c
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#define DWMCI_IDINTEN 0x090
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#define DWMCI_DSCADDR 0x094
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#define DWMCI_BUFADDR 0x098
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/* Registers to support IDMAC 64-bit address mode */
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#define DWMCI_DBADDRL 0x088
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#define DWMCI_DBADDRU 0x08c
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#define DWMCI_IDSTS64 0x090
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#define DWMCI_IDINTEN64 0x094
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#define DWMCI_DSCADDRL 0x098
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#define DWMCI_DSCADDRU 0x09c
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#define DWMCI_BUFADDRL 0x0a0
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#define DWMCI_BUFADDRU 0x0a4
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/* Interrupt Mask register */
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#define DWMCI_INTMSK_ALL 0xffffffff
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#define DWMCI_INTMSK_RE BIT(1)
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#define DWMCI_INTMSK_CDONE BIT(2)
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#define DWMCI_INTMSK_DTO BIT(3)
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#define DWMCI_INTMSK_TXDR BIT(4)
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#define DWMCI_INTMSK_RXDR BIT(5)
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#define DWMCI_INTMSK_RCRC BIT(6)
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#define DWMCI_INTMSK_DCRC BIT(7)
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#define DWMCI_INTMSK_RTO BIT(8)
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#define DWMCI_INTMSK_DRTO BIT(9)
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#define DWMCI_INTMSK_HTO BIT(10)
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#define DWMCI_INTMSK_FRUN BIT(11)
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#define DWMCI_INTMSK_HLE BIT(12)
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#define DWMCI_INTMSK_SBE BIT(13)
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#define DWMCI_INTMSK_ACD BIT(14)
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#define DWMCI_INTMSK_EBE BIT(15)
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/* Raw interrupt register */
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#define DWMCI_DATA_ERR (DWMCI_INTMSK_EBE | DWMCI_INTMSK_SBE | \
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DWMCI_INTMSK_HLE | DWMCI_INTMSK_FRUN | \
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DWMCI_INTMSK_EBE | DWMCI_INTMSK_DCRC)
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#define DWMCI_DATA_TOUT (DWMCI_INTMSK_HTO | DWMCI_INTMSK_DRTO)
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/* CTRL register */
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#define DWMCI_CTRL_RESET BIT(0)
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#define DWMCI_CTRL_FIFO_RESET BIT(1)
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#define DWMCI_CTRL_DMA_RESET BIT(2)
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#define DWMCI_DMA_EN BIT(5)
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#define DWMCI_CTRL_SEND_AS_CCSD BIT(10)
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#define DWMCI_IDMAC_EN BIT(25)
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#define DWMCI_RESET_ALL (DWMCI_CTRL_RESET | DWMCI_CTRL_FIFO_RESET |\
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DWMCI_CTRL_DMA_RESET)
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/* CMD register */
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#define DWMCI_CMD_RESP_EXP BIT(6)
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#define DWMCI_CMD_RESP_LENGTH BIT(7)
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#define DWMCI_CMD_CHECK_CRC BIT(8)
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#define DWMCI_CMD_DATA_EXP BIT(9)
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#define DWMCI_CMD_RW BIT(10)
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#define DWMCI_CMD_SEND_STOP BIT(12)
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#define DWMCI_CMD_ABORT_STOP BIT(14)
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#define DWMCI_CMD_PRV_DAT_WAIT BIT(13)
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#define DWMCI_CMD_UPD_CLK BIT(21)
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#define DWMCI_CMD_USE_HOLD_REG BIT(29)
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#define DWMCI_CMD_START BIT(31)
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/* CLKENA register */
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#define DWMCI_CLKEN_ENABLE BIT(0)
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#define DWMCI_CLKEN_LOW_PWR BIT(16)
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/* Card type register */
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#define DWMCI_CTYPE_1BIT 0
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#define DWMCI_CTYPE_4BIT BIT(0)
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#define DWMCI_CTYPE_8BIT BIT(16)
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/* Status register */
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#define DWMCI_FIFO_EMPTY BIT(2)
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#define DWMCI_FIFO_FULL BIT(3)
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#define DWMCI_BUSY BIT(9)
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#define DWMCI_FIFO_MASK 0x1fff
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#define DWMCI_FIFO_SHIFT 17
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/* FIFOTH register */
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#define MSIZE(x) ((x) << 28)
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#define RX_WMARK(x) ((x) << 16)
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#define TX_WMARK(x) (x)
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#define RX_WMARK_SHIFT 16
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#define RX_WMARK_MASK (0xfff << RX_WMARK_SHIFT)
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#define DWMCI_IDMAC_OWN BIT(31)
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#define DWMCI_IDMAC_CH BIT(4)
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#define DWMCI_IDMAC_FS BIT(3)
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#define DWMCI_IDMAC_LD BIT(2)
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/* Bus Mode register */
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#define DWMCI_BMOD_IDMAC_RESET BIT(0)
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#define DWMCI_BMOD_IDMAC_FB BIT(1)
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#define DWMCI_BMOD_IDMAC_EN BIT(7)
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/* UHS register */
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#define DWMCI_DDR_MODE BIT(16)
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/* Internal IDMAC interrupt defines */
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#define DWMCI_IDINTEN_RI BIT(1)
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#define DWMCI_IDINTEN_TI BIT(0)
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#define DWMCI_IDINTEN_MASK (DWMCI_IDINTEN_TI | DWMCI_IDINTEN_RI)
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/**
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* struct dwmci_idmac_regs - Offsets of IDMAC registers
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*
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* @dbaddrl: Descriptor base address, lower 32 bits
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* @dbaddru: Descriptor base address, upper 32 bits
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* @idsts: Internal DMA status
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* @idinten: Internal DMA interrupt enable
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* @dscaddrl: IDMAC descriptor address, lower 32 bits
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* @dscaddru: IDMAC descriptor address, upper 32 bits
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* @bufaddrl: Current data buffer address, lower 32 bits
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* @bufaddru: Current data buffer address, upper 32 bits
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*/
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struct dwmci_idmac_regs {
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u32 dbaddrl;
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u32 dbaddru;
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u32 idsts;
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u32 idinten;
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u32 dscaddrl;
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u32 dscaddru;
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u32 bufaddrl;
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u32 bufaddru;
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};
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/**
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* struct dwmci_host - Information about a designware MMC host
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*
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* @name: Device name
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* @ioaddr: Base I/O address of controller
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* @caps: Capabilities - see MMC_MODE_...
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* @clock: Current clock frequency (after internal divider), Hz
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* @bus_hz: Bus speed in Hz, if @get_mmc_clk() is NULL
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* @dev_index: Arbitrary device index for use by controller
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* @dev_id: Arbitrary device ID for use by controller
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* @buswidth: Bus width in bits (8 or 4)
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* @fifo_depth: Depth of FIFO, bytes (or 0 for automatic detection)
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* @mmc: Pointer to generic MMC structure for this device
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* @priv: Private pointer for use by controller
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* @clksel: (Optional) Platform function to run when speed/width is changed
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* @board_init: (Optional) Platform function to run on init
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* @cfg: Internal MMC configuration, for !CONFIG_BLK cases
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* @fifo_mode: Use FIFO mode (not DMA) to read and write data
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* @dma_64bit_address: Whether DMA supports 64-bit address mode or not
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* @regs: Registers that can vary for different DW MMC block versions
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*/
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struct dwmci_host {
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const char *name;
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void *ioaddr;
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unsigned int caps;
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unsigned int clock;
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unsigned int bus_hz;
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int dev_index;
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int dev_id;
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int buswidth;
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u32 fifo_depth;
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struct mmc *mmc;
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void *priv;
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int (*clksel)(struct dwmci_host *host);
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void (*board_init)(struct dwmci_host *host);
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/**
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* @get_mmc_clk: (Optional) Platform function to get/set a particular
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* MMC clock frequency
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*
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* @host: DWMMC host
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* @freq: Frequency the host is trying to achieve
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*
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* This is used to request the current clock frequency of the clock
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* that drives the DWMMC peripheral. The caller will then use this
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* information to work out the divider it needs to achieve the
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* required MMC bus clock frequency. If you want to handle the
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* clock external to DWMMC, use @freq to select the frequency and
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* return that value too. Then DWMMC will put itself in bypass mode.
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*/
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unsigned int (*get_mmc_clk)(struct dwmci_host *host, uint freq);
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#ifndef CONFIG_BLK
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struct mmc_config cfg;
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#endif
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bool fifo_mode;
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bool dma_64bit_address;
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const struct dwmci_idmac_regs *regs;
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};
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static inline void dwmci_writel(struct dwmci_host *host, int reg, u32 val)
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{
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writel(val, host->ioaddr + reg);
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}
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static inline void dwmci_writew(struct dwmci_host *host, int reg, u16 val)
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{
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writew(val, host->ioaddr + reg);
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}
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static inline void dwmci_writeb(struct dwmci_host *host, int reg, u8 val)
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{
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writeb(val, host->ioaddr + reg);
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}
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static inline u32 dwmci_readl(struct dwmci_host *host, int reg)
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{
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return readl(host->ioaddr + reg);
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}
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static inline u16 dwmci_readw(struct dwmci_host *host, int reg)
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{
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return readw(host->ioaddr + reg);
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}
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static inline u8 dwmci_readb(struct dwmci_host *host, int reg)
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{
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return readb(host->ioaddr + reg);
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}
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#ifdef CONFIG_BLK
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/**
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* dwmci_setup_cfg() - Set up the configuration for DWMMC
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* @cfg: Configuration structure to fill in (generally &plat->mmc)
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* @host: DWMMC host
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* @max_clk: Maximum supported clock speed in Hz (e.g. 150000000)
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* @min_clk: Minimum supported clock speed in Hz (e.g. 400000)
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*
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* This is used to set up a DWMMC device when you are using CONFIG_BLK.
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*
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* This should be called from your MMC driver's probe() method once you have
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* the information required.
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*
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* Generally your driver will have a platform data structure which holds both
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* the configuration (struct mmc_config) and the MMC device info (struct mmc).
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* For example:
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*
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* struct rockchip_mmc_plat {
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* struct mmc_config cfg;
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* struct mmc mmc;
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* };
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*
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* ...
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*
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* Inside U_BOOT_DRIVER():
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* .plat_auto = sizeof(struct rockchip_mmc_plat),
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*
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* To access platform data:
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* struct rockchip_mmc_plat *plat = dev_get_plat(dev);
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*
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* See rockchip_dw_mmc.c for an example.
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*/
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void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host,
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u32 max_clk, u32 min_clk);
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/**
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* dwmci_bind() - Set up a new MMC block device
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* @dev: Device to set up
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* @mmc: Pointer to mmc structure (normally &plat->mmc)
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* @cfg: Empty configuration structure (generally &plat->cfg). This is
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* normally all zeroes at this point. The only purpose of passing
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* this in is to set mmc->cfg to it.
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*
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* This is used to set up a DWMMC block device when you are using CONFIG_BLK.
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* It should be called from your driver's bind() method.
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*
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* See rockchip_dw_mmc.c for an example.
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*
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* Return: 0 if OK, -ve if the block device could not be created
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*/
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int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
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#else
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/**
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* add_dwmci() - Add a new DWMMC interface
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* @host: DWMMC host structure
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* @max_clk: Maximum supported clock speed in Hz (e.g. 150000000)
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* @min_clk: Minimum supported clock speed in Hz (e.g. 400000)
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*
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* This is used when you are not using CONFIG_BLK. Convert your driver over!
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*
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* Return: 0 if OK, -ve on error
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*/
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int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk);
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#endif /* !CONFIG_BLK */
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#ifdef CONFIG_DM_MMC
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/* Export the operations to drivers */
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int dwmci_probe(struct udevice *dev);
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extern const struct dm_mmc_ops dm_dwmci_ops;
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#endif
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#endif /* __DWMMC_HW_H */
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