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https://github.com/smaeul/u-boot.git
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
68 lines
1.7 KiB
C
68 lines
1.7 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
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* All rights reserved.
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*/
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#ifndef _FPGA_MANAGER_GEN5_H_
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#define _FPGA_MANAGER_GEN5_H_
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#define FPGAMGRREGS_STAT_MODE_MASK 0x7
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#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8
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#define FPGAMGRREGS_STAT_MSEL_LSB 3
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#define FPGAMGRREGS_CTRL_CFGWDTH_MASK BIT(9)
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#define FPGAMGRREGS_CTRL_AXICFGEN_MASK BIT(8)
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#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK BIT(2)
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#define FPGAMGRREGS_CTRL_NCE_MASK BIT(1)
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#define FPGAMGRREGS_CTRL_EN_MASK BIT(0)
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#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6
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#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK BIT(3)
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#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK BIT(2)
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#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK BIT(1)
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#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK BIT(0)
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/* FPGA Mode */
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#define FPGAMGRREGS_MODE_FPGAOFF 0x0
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#define FPGAMGRREGS_MODE_RESETPHASE 0x1
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#define FPGAMGRREGS_MODE_CFGPHASE 0x2
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#define FPGAMGRREGS_MODE_INITPHASE 0x3
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#define FPGAMGRREGS_MODE_USERMODE 0x4
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#define FPGAMGRREGS_MODE_UNKNOWN 0x5
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#ifndef __ASSEMBLY__
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struct socfpga_fpga_manager {
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/* FPGA Manager Module */
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u32 stat; /* 0x00 */
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u32 ctrl;
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u32 dclkcnt;
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u32 dclkstat;
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u32 gpo; /* 0x10 */
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u32 gpi;
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u32 misci; /* 0x18 */
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u32 _pad_0x1c_0x82c[517];
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/* Configuration Monitor (MON) Registers */
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u32 gpio_inten; /* 0x830 */
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u32 gpio_intmask;
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u32 gpio_inttype_level;
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u32 gpio_int_polarity;
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u32 gpio_intstatus; /* 0x840 */
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u32 gpio_raw_intstatus;
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u32 _pad_0x848;
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u32 gpio_porta_eoi;
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u32 gpio_ext_porta; /* 0x850 */
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u32 _pad_0x854_0x85c[3];
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u32 gpio_1s_sync; /* 0x860 */
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u32 _pad_0x864_0x868[2];
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u32 gpio_ver_id_code;
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u32 gpio_config_reg2; /* 0x870 */
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u32 gpio_config_reg1;
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};
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#endif /* __ASSEMBLY__ */
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#endif /* _FPGA_MANAGER_GEN5_H_ */
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