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db5741f7a8
Convert system manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get system manager base address from DT node instead of using #define. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
245 lines
6.3 KiB
C
245 lines
6.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016-2017 Intel Corporation
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*/
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#include <asm/io.h>
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#include <asm/arch/fpga_manager.h>
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#include <asm/arch/misc.h>
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#include <asm/arch/reset_manager.h>
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#include <asm/arch/system_manager.h>
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#include <common.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <wait_bit.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct bridge_cfg {
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int compat_id;
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u32 mask_noc;
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u32 mask_rstmgr;
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};
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static const struct bridge_cfg bridge_cfg_tbl[] = {
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{
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COMPAT_ALTERA_SOCFPGA_H2F_BRG,
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ALT_SYSMGR_NOC_H2F_SET_MSK,
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ALT_RSTMGR_BRGMODRST_H2F_SET_MSK,
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},
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{
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COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,
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ALT_SYSMGR_NOC_LWH2F_SET_MSK,
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ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK,
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},
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{
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COMPAT_ALTERA_SOCFPGA_F2H_BRG,
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ALT_SYSMGR_NOC_F2H_SET_MSK,
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ALT_RSTMGR_BRGMODRST_F2H_SET_MSK,
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},
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{
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COMPAT_ALTERA_SOCFPGA_F2SDR0,
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ALT_SYSMGR_NOC_F2SDR0_SET_MSK,
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ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK,
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},
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{
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COMPAT_ALTERA_SOCFPGA_F2SDR1,
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ALT_SYSMGR_NOC_F2SDR1_SET_MSK,
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ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK,
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},
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{
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COMPAT_ALTERA_SOCFPGA_F2SDR2,
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ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
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ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK,
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},
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};
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/* Disable the watchdog (toggle reset to watchdog) */
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void socfpga_watchdog_disable(void)
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{
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/* assert reset for watchdog */
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setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER1MODRST,
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ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
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}
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/* Release NOC ddr scheduler from reset */
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void socfpga_reset_deassert_noc_ddr_scheduler(void)
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{
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clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_BRGMODRST,
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ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK);
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}
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static int get_bridge_init_val(const void *blob, int compat_id)
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{
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int node;
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node = fdtdec_next_compatible(blob, 0, compat_id);
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if (node < 0)
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return 0;
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return fdtdec_get_uint(blob, node, "init-val", 0);
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}
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/* Enable bridges (hps2fpga, lwhps2fpga, fpga2hps, fpga2sdram) per handoff */
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int socfpga_reset_deassert_bridges_handoff(void)
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{
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u32 mask_noc = 0, mask_rstmgr = 0;
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int i;
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for (i = 0; i < ARRAY_SIZE(bridge_cfg_tbl); i++) {
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if (get_bridge_init_val(gd->fdt_blob,
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bridge_cfg_tbl[i].compat_id)) {
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mask_noc |= bridge_cfg_tbl[i].mask_noc;
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mask_rstmgr |= bridge_cfg_tbl[i].mask_rstmgr;
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}
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}
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/* clear idle request to all bridges */
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setbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_A10_NOC_IDLEREQ_CLR,
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mask_noc);
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/* Release bridges from reset state per handoff value */
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clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_BRGMODRST,
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mask_rstmgr);
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/* Poll until all idleack to 0, timeout at 1000ms */
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return wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() +
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SYSMGR_A10_NOC_IDLEACK),
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mask_noc, false, 1000, false);
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}
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/* Release L4 OSC1 Watchdog Timer 0 from reset through reset manager */
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void socfpga_reset_deassert_osc1wd0(void)
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{
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clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER1MODRST,
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ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
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}
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/*
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* Assert or de-assert SoCFPGA reset manager reset.
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*/
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void socfpga_per_reset(u32 reset, int set)
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{
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unsigned long reg;
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u32 rstmgr_bank = RSTMGR_BANK(reset);
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switch (rstmgr_bank) {
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case 0:
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reg = RSTMGR_A10_MPUMODRST;
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break;
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case 1:
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reg = RSTMGR_A10_PER0MODRST;
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break;
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case 2:
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reg = RSTMGR_A10_PER1MODRST;
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break;
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case 3:
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reg = RSTMGR_A10_BRGMODRST;
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break;
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case 4:
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reg = RSTMGR_A10_SYSMODRST;
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break;
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default:
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return;
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}
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if (set)
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setbits_le32(socfpga_get_rstmgr_addr() + reg,
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1 << RSTMGR_RESET(reset));
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else
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clrbits_le32(socfpga_get_rstmgr_addr() + reg,
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1 << RSTMGR_RESET(reset));
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}
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/*
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* Assert reset on every peripheral but L4WD0.
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* Watchdog must be kept intact to prevent glitches
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* and/or hangs.
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* For the Arria10, we disable all the peripherals except L4 watchdog0,
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* L4 Timer 0, and ECC.
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*/
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void socfpga_per_reset_all(void)
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{
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const u32 l4wd0 = (1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)) |
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(1 << RSTMGR_RESET(SOCFPGA_RESET(L4SYSTIMER0))));
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unsigned mask_ecc_ocp =
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ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK |
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ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK |
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ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK |
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ALT_RSTMGR_PER0MODRST_USBECC0_SET_MSK |
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ALT_RSTMGR_PER0MODRST_USBECC1_SET_MSK |
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ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK |
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ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK |
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ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK;
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/* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */
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writel(~l4wd0, socfpga_get_rstmgr_addr() + RSTMGR_A10_PER1MODRST);
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setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER0MODRST,
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~mask_ecc_ocp);
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/* Finally disable the ECC_OCP */
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setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER0MODRST,
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mask_ecc_ocp);
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}
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int socfpga_bridges_reset(void)
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{
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int ret;
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/* Disable all the bridges (hps2fpga, lwhps2fpga, fpga2hps,
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fpga2sdram) */
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/* set idle request to all bridges */
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writel(ALT_SYSMGR_NOC_H2F_SET_MSK |
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ALT_SYSMGR_NOC_LWH2F_SET_MSK |
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ALT_SYSMGR_NOC_F2H_SET_MSK |
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ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
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ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
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ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
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socfpga_get_sysmgr_addr() + SYSMGR_A10_NOC_IDLEREQ_SET);
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/* Enable the NOC timeout */
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writel(ALT_SYSMGR_NOC_TMO_EN_SET_MSK,
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socfpga_get_sysmgr_addr() + SYSMGR_A10_NOC_TIMEOUT);
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/* Poll until all idleack to 1 */
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ret = wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() +
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SYSMGR_A10_NOC_IDLEACK),
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ALT_SYSMGR_NOC_H2F_SET_MSK |
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ALT_SYSMGR_NOC_LWH2F_SET_MSK |
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ALT_SYSMGR_NOC_F2H_SET_MSK |
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ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
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ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
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ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
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true, 10000, false);
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if (ret)
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return ret;
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/* Poll until all idlestatus to 1 */
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ret = wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() +
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SYSMGR_A10_NOC_IDLESTATUS),
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ALT_SYSMGR_NOC_H2F_SET_MSK |
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ALT_SYSMGR_NOC_LWH2F_SET_MSK |
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ALT_SYSMGR_NOC_F2H_SET_MSK |
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ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
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ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
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ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
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true, 10000, false);
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if (ret)
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return ret;
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/* Put all bridges (except NOR DDR scheduler) into reset state */
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setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_BRGMODRST,
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(ALT_RSTMGR_BRGMODRST_H2F_SET_MSK |
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ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK |
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ALT_RSTMGR_BRGMODRST_F2H_SET_MSK |
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ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK |
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ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK |
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ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK));
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/* Disable NOC timeout */
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writel(0, socfpga_get_sysmgr_addr() + SYSMGR_A10_NOC_TIMEOUT);
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return 0;
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}
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