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5cd4a355e0
Add the DeveloperBox 96boards EE support. This board is also known as Socionext SynQuacer E-Series. It contians one "SC2A11" SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots, 3 PCIe slots (1 4x port and 2 1x ports which are expanded via PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard MicroATX Form Factor. For more information, see this page; https://www.96boards.org/product/developerbox/ Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
147 lines
2.9 KiB
C
147 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* u-boot/board/socionext/developerbox/developerbox.c
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*
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* Copyright (C) 2016-2017 Socionext Inc.
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* Copyright (C) 2021 Linaro Ltd.
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*/
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#include <asm/types.h>
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#include <asm/armv8/mmu.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <common.h>
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#include <env_internal.h>
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#include <fdt_support.h>
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#include <log.h>
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static struct mm_region sc2a11_mem_map[] = {
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{
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_OUTER_SHARE
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}, {
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/* 1st DDR block */
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.virt = 0x80000000UL,
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.phys = 0x80000000UL,
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.size = PHYS_SDRAM_SIZE,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_OUTER_SHARE
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}, {
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/* 2nd DDR place holder */
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0,
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}, {
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/* 3rd DDR place holder */
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0,
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = sc2a11_mem_map;
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#define DDR_REGION_INDEX(i) (1 + (i))
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#define MAX_DDR_REGIONS 3
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struct draminfo_entry {
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u64 base;
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u64 size;
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};
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struct draminfo {
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u32 nr_regions;
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u32 reserved;
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struct draminfo_entry entry[3];
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};
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struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE;
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DECLARE_GLOBAL_DATA_PTR;
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#define LOAD_OFFSET 0x100
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/*
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* Miscellaneous platform dependent initialisations
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*/
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int board_init(void)
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{
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gd->bd->bi_boot_params = CONFIG_SYS_LOAD_ADDR + LOAD_OFFSET;
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gd->env_addr = (ulong)&default_environment[0];
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return 0;
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}
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int ft_board_setup(void *blob, struct bd_info *bd)
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{
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/* Remove SPI NOR and I2C0 for making DT compatible with EDK2 */
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fdt_del_node_and_alias(blob, "spi_nor");
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fdt_del_node_and_alias(blob, "i2c0");
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return 0;
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}
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/*
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* DRAM configuration
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*/
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int dram_init(void)
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{
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struct draminfo_entry *ent = synquacer_draminfo->entry;
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struct mm_region *mr;
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int i, ri;
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if (synquacer_draminfo->nr_regions < 1) {
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log_err("Failed to get correct DRAM information\n");
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return -1;
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}
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/*
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* U-Boot RAM size must be under the first DRAM region so that it doesn't
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* access secure memory which is at the end of the first DRAM region.
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*/
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gd->ram_size = ent[0].size;
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/* Update memory region maps */
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for (i = 0; i < synquacer_draminfo->nr_regions; i++) {
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if (i >= MAX_DDR_REGIONS)
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break;
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ri = DDR_REGION_INDEX(i);
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mem_map[ri].phys = ent[i].base;
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mem_map[ri].size = ent[i].size;
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if (i == 0)
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continue;
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mr = &mem_map[DDR_REGION_INDEX(0)];
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mem_map[ri].virt = mr->virt + mr->size;
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mem_map[ri].attrs = mr->attrs;
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}
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return 0;
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}
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int dram_init_banksize(void)
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{
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struct draminfo_entry *ent = synquacer_draminfo->entry;
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int i;
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for (i = 0; i < ARRAY_SIZE(gd->bd->bi_dram); i++) {
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if (i < synquacer_draminfo->nr_regions) {
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debug("%s: dram[%d] = %llx@%llx\n", __func__, i, ent[i].size, ent[i].base);
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gd->bd->bi_dram[i].start = ent[i].base;
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gd->bd->bi_dram[i].size = ent[i].size;
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}
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}
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return 0;
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}
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int print_cpuinfo(void)
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{
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printf("CPU: SC2A11:Cortex-A53 MPCore 24cores\n");
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return 0;
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}
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