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857b9cb69f
Though nios2-generic board meant to be a template, it is helpful to be able to test on a real hardware. As the nios2 linux is developed and tested on a 3c120 FPGA based Golden Hardware Reference Design, it makes sense to rebase nios2-generic on this FPGA design. Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
90 lines
2.9 KiB
C
90 lines
2.9 KiB
C
/*
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* This header is generated by sopc2dts
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* Sopc2dts is written by Walter Goossens <waltergoossens@home.nl>
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* in cooperation with the nios2 community <Nios2-dev@sopc.et.ntust.edu.tw>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _CUSTOM_FPGA_H_
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#define _CUSTOM_FPGA_H_
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/* generated from qsys_ghrd_3c120.sopcinfo */
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/* Dumping slaves of cpu.data_master */
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/* cpu.jtag_debug_module is a altera_nios2_qsys */
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#define CONFIG_SYS_CLK_FREQ 125000000
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#define CONFIG_SYS_DCACHE_SIZE 32768
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#define CONFIG_SYS_DCACHELINE_SIZE 32
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#define CONFIG_SYS_ICACHELINE_SIZE 32
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#define CONFIG_SYS_EXCEPTION_ADDR 0xd0000020
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#define CONFIG_SYS_ICACHE_SIZE 32768
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#define CONFIG_SYS_RESET_ADDR 0xc2800000
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#define IO_REGION_BASE 0xE0000000
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/* pb_cpu_to_ddr2_bot.s0 is a altera_avalon_mm_bridge */
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/* Dumping slaves of pb_cpu_to_ddr2_bot.m0 */
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/* ddr2_bot.s1 is a altmemddr2 */
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#define CONFIG_SYS_SDRAM_BASE 0xD0000000
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#define CONFIG_SYS_SDRAM_SIZE 0x08000000
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/* pb_cpu_to_io.s0 is a altera_avalon_mm_bridge */
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/* Dumping slaves of pb_cpu_to_io.m0 */
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/* timer_1ms.s1 is a altera_avalon_timer */
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#define CONFIG_SYS_TIMER_IRQ 11
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#define CONFIG_SYS_TIMER_FREQ 125000000
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#define CONFIG_SYS_TIMER_BASE 0xE8400000
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/* sysid.control_slave is a altera_avalon_sysid_qsys */
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#define CONFIG_SYS_SYSID_BASE 0xE8004D40
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/* jtag_uart.avalon_jtag_slave is a altera_avalon_jtag_uart */
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#define CONFIG_SYS_JTAG_UART_BASE 0xE8004D50
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/* tse_mac.control_port is a triple_speed_ethernet */
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#define CONFIG_SYS_ALTERA_TSE_RX_FIFO 2048
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#define CONFIG_SYS_ALTERA_TSE_SGDMA_TX_BASE 0xE8004800
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#define CONFIG_SYS_ALTERA_TSE_SGDMA_RX_BASE 0xE8004400
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#define CONFIG_SYS_ALTERA_TSE_TX_FIFO 2048
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#define CONFIG_SYS_ALTERA_TSE_DESC_SIZE 0x00002000
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#define CONFIG_SYS_ALTERA_TSE_MAC_BASE 0xE8004000
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#define CONFIG_SYS_ALTERA_TSE_DESC_BASE 0xE8002000
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#define CONFIG_ALTERA_TSE
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#define CONFIG_MII
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#define CONFIG_CMD_MII
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#define CONFIG_SYS_ALTERA_TSE_PHY_ADDR 18
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#define CONFIG_SYS_ALTERA_TSE_FLAGS 1
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/* uart.s1 is a altera_avalon_uart */
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#define CONFIG_SYS_UART_BAUD 115200
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#define CONFIG_SYS_UART_BASE 0xE8004C80
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#define CONFIG_SYS_UART_FREQ 62500000
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/* user_led_pio_8out.s1 is a altera_avalon_pio */
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#define USER_LED_PIO_8OUT_BASE 0xE8004CC0
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/* user_dipsw_pio_8in.s1 is a altera_avalon_pio */
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#define USER_DIPSW_PIO_8IN_BASE 0xE8004CE0
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#define USER_DIPSW_PIO_8IN_IRQ 8
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/* user_pb_pio_4in.s1 is a altera_avalon_pio */
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#define USER_PB_PIO_4IN_BASE 0xE8004D00
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#define USER_PB_PIO_4IN_IRQ 9
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/* cfi_flash_64m.uas is a altera_generic_tristate_controller */
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#define CFI_FLASH_64M_BASE 0xE0000000
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/* ext_flash.s1 is a altera_avalon_cfi_flash */
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#define CONFIG_SYS_FLASH_BASE CFI_FLASH_64M_BASE
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
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#define CONFIG_SYS_FLASH_PROTECTION
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 512
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#endif /* _CUSTOM_FPGA_H_ */
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