mirror of
https://github.com/smaeul/u-boot.git
synced 2025-10-30 19:48:19 +00:00
702841b56e
Remove <common.h> from all powerpc architecture files and when needed add missing include files directly. This typically involves using <asm/u-boot.h> instead due to the difficult nested structure of the PowerPC includes themselves. Signed-off-by: Tom Rini <trini@konsulko.com>
100 lines
4.0 KiB
C
100 lines
4.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* Copyright 2009-2011 Freescale Semiconductor, Inc.
|
|
*/
|
|
|
|
#include <asm/fsl_serdes.h>
|
|
#include <asm/processor.h>
|
|
#include <asm/io.h>
|
|
#include "fsl_corenet_serdes.h"
|
|
|
|
/*
|
|
* Note: For P5040, the fourth SerDes bank (with two lanes) is on SerDes2, but
|
|
* U-Boot only supports one SerDes controller. Therefore, we ignore bank 4 in
|
|
* this table. This works because most of the SerDes code is for errata
|
|
* work-arounds, and there are no P5040 errata that effect bank 4.
|
|
*/
|
|
|
|
static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
|
|
[0x00] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
|
|
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC1,
|
|
SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
|
|
XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, /* SATA1, SATA2, */ },
|
|
[0x01] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
|
|
SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, XAUI_FM1, XAUI_FM1,
|
|
XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2, XAUI_FM2,
|
|
XAUI_FM2, /* SATA1, SATA2 */ },
|
|
[0x02] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SGMII_FM1_DTSEC3,
|
|
SGMII_FM1_DTSEC4, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
|
|
XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2,
|
|
XAUI_FM2, XAUI_FM2, /* SATA1, SATA2 */ },
|
|
[0x03] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SGMII_FM2_DTSEC1,
|
|
SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
|
|
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
|
|
SGMII_FM1_DTSEC4, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
|
|
/* SATA1, SATA2 */ },
|
|
[0x04] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE3, SGMII_FM2_DTSEC1,
|
|
SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
|
|
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
|
|
SGMII_FM1_DTSEC4, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
|
|
/* SATA1, SATA2 */ },
|
|
[0x05] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE3, SGMII_FM1_DTSEC3,
|
|
SGMII_FM1_DTSEC4, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
|
|
XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2,
|
|
XAUI_FM2, XAUI_FM2, /* SATA1, SATA2 */ },
|
|
[0x06] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1,
|
|
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC1,
|
|
SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
|
|
XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, /* SATA1, SATA2 */ },
|
|
[0x07] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1,
|
|
SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, XAUI_FM1, XAUI_FM1,
|
|
XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2, XAUI_FM2,
|
|
XAUI_FM2, /* SATA1, SATA2 */ },
|
|
[0x11] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
|
|
AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
|
|
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2,
|
|
/* NONE, NONE */ },
|
|
[0x15] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
|
|
AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
|
|
NONE, NONE, SATA1, SATA2, /* NONE, NONE */ },
|
|
[0x2a] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
|
|
AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
|
|
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM2, XAUI_FM2,
|
|
XAUI_FM2, XAUI_FM2, /* NONE, NONE */ },
|
|
[0x34] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM1_DTSEC1,
|
|
SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
|
|
AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
|
|
NONE, SATA1, SATA2, /* NONE, NONE */ },
|
|
[0x35] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2,
|
|
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1,
|
|
XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2,
|
|
/* NONE, NONE */ },
|
|
[0x36] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM1_DTSEC1,
|
|
SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
|
|
AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
|
|
NONE, SATA1, SATA2, /* NONE, NONE */ },
|
|
};
|
|
|
|
enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
|
|
{
|
|
if (!serdes_lane_enabled(lane))
|
|
return NONE;
|
|
|
|
return serdes_cfg_tbl[cfg][lane];
|
|
}
|
|
|
|
int is_serdes_prtcl_valid(u32 prtcl)
|
|
{
|
|
int i;
|
|
|
|
if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
|
|
return 0;
|
|
|
|
for (i = 0; i < SRDS_MAX_LANES; i++) {
|
|
if (serdes_cfg_tbl[prtcl][i] != NONE)
|
|
return 1;
|
|
}
|
|
|
|
return 0;
|
|
}
|