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079edb913d
Bits MPCTL[MFN] and MPCTL[MFD] were not fully covered. Signed-off-by: Jens Gehrlein <sew_s@tqs.de>
101 lines
2.4 KiB
C
101 lines
2.4 KiB
C
/*
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* (C) Copyright 2007
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* Sascha Hauer, Pengutronix
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/mx31-regs.h>
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static u32 mx31_decode_pll(u32 reg, u32 infreq)
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{
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u32 mfi = (reg >> 10) & 0xf;
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u32 mfn = reg & 0x3ff;
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u32 mfd = (reg >> 16) & 0x3ff;
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u32 pd = (reg >> 26) & 0xf;
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mfi = mfi <= 5 ? 5 : mfi;
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mfd += 1;
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pd += 1;
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return ((2 * (infreq >> 10) * (mfi * mfd + mfn)) /
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(mfd * pd)) << 10;
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}
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static u32 mx31_get_mpl_dpdgck_clk(void)
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{
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u32 infreq;
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if ((__REG(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM)
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infreq = CONFIG_MX31_CLK32 * 1024;
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else
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infreq = CONFIG_MX31_HCLK_FREQ;
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return mx31_decode_pll(__REG(CCM_MPCTL), infreq);
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}
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static u32 mx31_get_mcu_main_clk(void)
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{
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/* For now we assume mpl_dpdgck_clk == mcu_main_clk
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* which should be correct for most boards
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*/
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return mx31_get_mpl_dpdgck_clk();
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}
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u32 mx31_get_ipg_clk(void)
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{
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u32 freq = mx31_get_mcu_main_clk();
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u32 pdr0 = __REG(CCM_PDR0);
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freq /= ((pdr0 >> 3) & 0x7) + 1;
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freq /= ((pdr0 >> 6) & 0x3) + 1;
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return freq;
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}
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void mx31_dump_clocks(void)
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{
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u32 cpufreq = mx31_get_mcu_main_clk();
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printf("mx31 cpu clock: %dMHz\n",cpufreq / 1000000);
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printf("ipg clock : %dHz\n", mx31_get_ipg_clk());
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}
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void mx31_gpio_mux(unsigned long mode)
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{
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unsigned long reg, shift, tmp;
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reg = IOMUXC_BASE + (mode & 0x1fc);
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shift = (~mode & 0x3) * 8;
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tmp = __REG(reg);
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tmp &= ~(0xff << shift);
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tmp |= ((mode >> IOMUX_MODE_POS) & 0xff) << shift;
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__REG(reg) = tmp;
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}
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#if defined(CONFIG_DISPLAY_CPUINFO)
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int print_cpuinfo (void)
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{
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printf("CPU: Freescale i.MX31 at %d MHz\n",
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mx31_get_mcu_main_clk() / 1000000);
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return 0;
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}
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#endif
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