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54e1aa236f
Add support for the Variscite VAR-SOM-IMX93 evaluation kit. The SoM consists of an NXP iMX93 dual A55 CPU. The SoM is mounted on a Variscite Symphony SBC. Signed-off-by: Mathieu Othacehe <m.othacehe@gmail.com>
84 lines
2.5 KiB
C
84 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2023 Variscite Ltd.
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*
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*/
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#ifndef _MX9_VAR_EEPROM_H_
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#define _MX9_VAR_EEPROM_H_
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#ifdef CONFIG_ARCH_IMX9
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#include <asm/arch-imx9/ddr.h>
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#endif
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#define VAR_SOM_EEPROM_MAGIC 0x4D58 /* == HEX("MX") */
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#define VAR_SOM_EEPROM_I2C_ADDR 0x52
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/* Optional SOM features */
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#define VAR_EEPROM_F_WIFI BIT(0)
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#define VAR_EEPROM_F_ETH BIT(1)
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#define VAR_EEPROM_F_AUDIO BIT(2)
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/* SOM storage types */
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enum som_storage {
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SOM_STORAGE_EMMC,
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SOM_STORAGE_NAND,
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SOM_STORAGE_UNDEFINED,
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};
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/* Number of DRAM adjustment tables */
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#define DRAM_TABLE_NUM 7
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struct __packed var_eeprom
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{
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u16 magic; /* 00-0x00 - magic number */
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u8 partnum[8]; /* 02-0x02 - part number */
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u8 assembly[10]; /* 10-0x0a - assembly number */
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u8 date[9]; /* 20-0x14 - build date */
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u8 mac[6]; /* 29-0x1d - MAC address */
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u8 somrev; /* 35-0x23 - SOM revision */
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u8 version; /* 36-0x24 - EEPROM version */
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u8 features; /* 37-0x25 - SOM features */
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u8 dramsize; /* 38-0x26 - DRAM size */
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u8 reserved[5]; /* 39 0x27 - reserved */
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u32 ddr_crc32; /* 44-0x2c - CRC32 of DDR DATAi */
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u16 ddr_vic; /* 48-0x30 - DDR VIC PN */
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u16 off[DRAM_TABLE_NUM + 1]; /* 50-0x32 - DRAM table offsets */
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};
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#define VAR_EEPROM_DATA ((struct var_eeprom *)VAR_EEPROM_DRAM_START)
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#define VAR_CARRIER_EEPROM_MAGIC 0x5643 /* == HEX("VC") */
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#define CARRIER_REV_LEN 16
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struct __packed var_carrier_eeprom
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{
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u16 magic; /* 00-0x00 - magic number */
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u8 struct_ver; /* 01-0x01 - EEPROM structure version */
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u8 carrier_rev[CARRIER_REV_LEN]; /* 02-0x02 - carrier board revision */
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u32 crc; /* 10-0x0a - checksum */
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};
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static inline int var_eeprom_is_valid(struct var_eeprom *ep)
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{
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if (htons(ep->magic) != VAR_SOM_EEPROM_MAGIC) {
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debug("Invalid EEPROM magic 0x%x, expected 0x%x\n",
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htons(ep->magic), VAR_SOM_EEPROM_MAGIC);
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return 0;
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}
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return 1;
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}
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int var_eeprom_read_header(struct var_eeprom *e);
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int var_eeprom_get_dram_size(struct var_eeprom *e, phys_size_t *size);
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int var_eeprom_get_mac(struct var_eeprom *e, u8 *mac);
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void var_eeprom_print_prod_info(struct var_eeprom *e);
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int var_carrier_eeprom_read(const char *bus_name, int addr, struct var_carrier_eeprom *ep);
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int var_carrier_eeprom_is_valid(struct var_carrier_eeprom *ep);
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void var_carrier_eeprom_get_revision(struct var_carrier_eeprom *ep, char *rev, size_t size);
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#endif /* _MX9_VAR_EEPROM_H_ */
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