mirror of
https://github.com/smaeul/u-boot.git
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03de305ec4
As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
272 lines
9.1 KiB
C
272 lines
9.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* (C) Copyright 2022 - Analog Devices, Inc.
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*
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* Written and/or maintained by Timesys Corporation
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*
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* Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
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* Contact: Greg Malysa <greg.malysa@timesys.com>
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*
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*/
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#ifndef DT_BINDINGS_CLOCK_ADI_SC5XX_CLOCK_H
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#define DT_BINDINGS_CLOCK_ADI_SC5XX_CLOCK_H
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//ADSP-SC594
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#define ADSP_SC594_CLK_DUMMY 0
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#define ADSP_SC594_CLK_SYS_CLKIN0 1
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#define ADSP_SC594_CLK_SYS_CLKIN1 2
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#define ADSP_SC594_CLK_CGU1_IN 3
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#define ADSP_SC594_CLK_CGU0_PLL_IN 4
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#define ADSP_SC594_CLK_CGU1_PLL_IN 5
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#define ADSP_SC594_CLK_CGU0_VCO_OUT 6
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#define ADSP_SC594_CLK_CGU1_VCO_OUT 7
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#define ADSP_SC594_CLK_CGU0_PLLCLK 8
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#define ADSP_SC594_CLK_CGU1_PLLCLK 9
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#define ADSP_SC594_CLK_CGU0_CDIV 10
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#define ADSP_SC594_CLK_CGU0_SYSCLK 11
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#define ADSP_SC594_CLK_CGU0_DDIV 12
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#define ADSP_SC594_CLK_CGU0_ODIV 13
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#define ADSP_SC594_CLK_CGU0_S0SELDIV 14
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#define ADSP_SC594_CLK_CGU0_S1SELDIV 15
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#define ADSP_SC594_CLK_CGU0_S1SELEXDIV 16
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#define ADSP_SC594_CLK_CGU0_S1SEL 17
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#define ADSP_SC594_CLK_CGU1_CDIV 18
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#define ADSP_SC594_CLK_CGU1_SYSCLK 19
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#define ADSP_SC594_CLK_CGU1_DDIV 20
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#define ADSP_SC594_CLK_CGU1_ODIV 21
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#define ADSP_SC594_CLK_CGU1_S0SELDIV 22
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#define ADSP_SC594_CLK_CGU1_S1SELDIV 23
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#define ADSP_SC594_CLK_CGU1_S1SELEXDIV 24
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#define ADSP_SC594_CLK_CGU1_S1SEL 25
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#define ADSP_SC594_CLK_CGU0_CCLK0 26
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#define ADSP_SC594_CLK_CGU0_CCLK1 27
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#define ADSP_SC594_CLK_CGU0_OCLK 28
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#define ADSP_SC594_CLK_CGU0_DCLK 29
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#define ADSP_SC594_CLK_CGU0_SCLK1 30
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#define ADSP_SC594_CLK_CGU0_SCLK0 31
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#define ADSP_SC594_CLK_CGU1_CCLK0 32
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#define ADSP_SC594_CLK_CGU1_CCLK1 33
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#define ADSP_SC594_CLK_CGU1_OCLK 34
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#define ADSP_SC594_CLK_CGU1_DCLK 35
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#define ADSP_SC594_CLK_CGU1_SCLK1 36
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#define ADSP_SC594_CLK_CGU1_SCLK0 37
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#define ADSP_SC594_CLK_SHARC0_SEL 38
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#define ADSP_SC594_CLK_SHARC1_SEL 39
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#define ADSP_SC594_CLK_ARM_SEL 40
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#define ADSP_SC594_CLK_CDU_DDR_SEL 41
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#define ADSP_SC594_CLK_CAN_SEL 42
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#define ADSP_SC594_CLK_SPDIF_SEL 43
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#define ADSP_SC594_CLK_RESERVED_SEL 44
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#define ADSP_SC594_CLK_GIGE_SEL 45
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#define ADSP_SC594_CLK_LP_SEL 46
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#define ADSP_SC594_CLK_LPDDR_SEL 47
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#define ADSP_SC594_CLK_OSPI_SEL 48
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#define ADSP_SC594_CLK_TRACE_SEL 49
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#define ADSP_SC594_CLK_SHARC0 50
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#define ADSP_SC594_CLK_SHARC1 51
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#define ADSP_SC594_CLK_ARM 52
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#define ADSP_SC594_CLK_CDU_DDR 53
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#define ADSP_SC594_CLK_CAN 54
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#define ADSP_SC594_CLK_SPDIF 55
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#define ADSP_SC594_CLK_SPI 56
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#define ADSP_SC594_CLK_GIGE 57
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#define ADSP_SC594_CLK_LP 58
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#define ADSP_SC594_CLK_LPDDR 59
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#define ADSP_SC594_CLK_OSPI 60
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#define ADSP_SC594_CLK_TRACE 61
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#define ADSP_SC594_CLK_END 62
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//ADSP-SC598
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#define ADSP_SC598_CLK_DUMMY 0
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#define ADSP_SC598_CLK_SYS_CLKIN0 1
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#define ADSP_SC598_CLK_SYS_CLKIN1 2
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#define ADSP_SC598_CLK_CGU0_PLL_IN 3
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#define ADSP_SC598_CLK_CGU0_VCO_OUT 4
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#define ADSP_SC598_CLK_CGU0_PLLCLK 5
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#define ADSP_SC598_CLK_CGU1_IN 6
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#define ADSP_SC598_CLK_CGU1_PLL_IN 7
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#define ADSP_SC598_CLK_CGU1_VCO_OUT 8
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#define ADSP_SC598_CLK_CGU1_PLLCLK 9
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#define ADSP_SC598_CLK_CGU0_CDIV 10
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#define ADSP_SC598_CLK_CGU0_SYSCLK 11
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#define ADSP_SC598_CLK_CGU0_DDIV 12
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#define ADSP_SC598_CLK_CGU0_ODIV 13
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#define ADSP_SC598_CLK_CGU0_S0SELDIV 14
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#define ADSP_SC598_CLK_CGU0_S1SELDIV 15
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#define ADSP_SC598_CLK_CGU0_S1SELEXDIV 16
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#define ADSP_SC598_CLK_CGU0_S1SEL 17
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#define ADSP_SC598_CLK_CGU1_CDIV 18
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#define ADSP_SC598_CLK_CGU1_SYSCLK 19
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#define ADSP_SC598_CLK_CGU1_DDIV 20
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#define ADSP_SC598_CLK_CGU1_ODIV 21
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#define ADSP_SC598_CLK_CGU1_S0SELDIV 22
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#define ADSP_SC598_CLK_CGU1_S1SELDIV 23
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#define ADSP_SC598_CLK_CGU1_S0SELEXDIV 24
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#define ADSP_SC598_CLK_CGU1_S1SELEXDIV 25
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#define ADSP_SC598_CLK_CGU1_S0SEL 26
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#define ADSP_SC598_CLK_CGU1_S1SEL 27
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#define ADSP_SC598_CLK_CGU0_CCLK2 28
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#define ADSP_SC598_CLK_CGU0_CCLK0 29
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#define ADSP_SC598_CLK_CGU0_OCLK 30
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#define ADSP_SC598_CLK_CGU0_DCLK 31
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#define ADSP_SC598_CLK_CGU0_SCLK1 32
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#define ADSP_SC598_CLK_CGU0_SCLK0 33
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#define ADSP_SC598_CLK_CGU1_CCLK0 34
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#define ADSP_SC598_CLK_CGU1_OCLK 35
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#define ADSP_SC598_CLK_CGU1_DCLK 36
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#define ADSP_SC598_CLK_CGU1_SCLK1 37
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#define ADSP_SC598_CLK_CGU1_SCLK0 38
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#define ADSP_SC598_CLK_CGU1_CCLK2 39
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#define ADSP_SC598_CLK_DCLK0_HALF 40
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#define ADSP_SC598_CLK_DCLK1_HALF 41
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#define ADSP_SC598_CLK_CGU1_SCLK1_HALF 42
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#define ADSP_SC598_CLK_SHARC0_SEL 43
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#define ADSP_SC598_CLK_SHARC1_SEL 44
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#define ADSP_SC598_CLK_ARM_SEL 45
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#define ADSP_SC598_CLK_CDU_DDR_SEL 46
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#define ADSP_SC598_CLK_CAN_SEL 47
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#define ADSP_SC598_CLK_SPDIF_SEL 48
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#define ADSP_SC598_CLK_SPI_SEL 49
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#define ADSP_SC598_CLK_GIGE_SEL 50
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#define ADSP_SC598_CLK_LP_SEL 51
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#define ADSP_SC598_CLK_LP_DDR_SEL 52
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#define ADSP_SC598_CLK_OSPI_REFCLK_SEL 53
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#define ADSP_SC598_CLK_TRACE_SEL 54
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#define ADSP_SC598_CLK_EMMC_SEL 55
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#define ADSP_SC598_CLK_EMMC_TIMER_QMC_SEL 56
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#define ADSP_SC598_CLK_SHARC0 57
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#define ADSP_SC598_CLK_SHARC1 58
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#define ADSP_SC598_CLK_ARM 59
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#define ADSP_SC598_CLK_CDU_DDR 60
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#define ADSP_SC598_CLK_CAN 61
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#define ADSP_SC598_CLK_SPDIF 62
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#define ADSP_SC598_CLK_SPI 63
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#define ADSP_SC598_CLK_GIGE 64
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#define ADSP_SC598_CLK_LP 65
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#define ADSP_SC598_CLK_LP_DDR 66
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#define ADSP_SC598_CLK_OSPI_REFCLK 67
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#define ADSP_SC598_CLK_TRACE 68
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#define ADSP_SC598_CLK_EMMC 69
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#define ADSP_SC598_CLK_EMMC_TIMER_QMC 70
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#define ADSP_SC598_CLK_3PLL_PLL_IN 71
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#define ADSP_SC598_CLK_3PLL_VCO_OUT 72
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#define ADSP_SC598_CLK_3PLL_PLLCLK 73
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#define ADSP_SC598_CLK_3PLL_DDIV 74
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#define ADSP_SC598_CLK_DDR 75
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#define ADSP_SC598_CLK_END 76
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//ADSP-SC58X
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#define ADSP_SC58X_CLK_DUMMY 0
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#define ADSP_SC58X_CLK_SYS_CLKIN0 1
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#define ADSP_SC58X_CLK_SYS_CLKIN1 2
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#define ADSP_SC58X_CLK_CGU0_PLL_IN 3
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#define ADSP_SC58X_CLK_CGU0_VCO_OUT 4
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#define ADSP_SC58X_CLK_CGU0_PLLCLK 5
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#define ADSP_SC58X_CLK_CGU1_IN 6
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#define ADSP_SC58X_CLK_CGU1_PLL_IN 7
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#define ADSP_SC58X_CLK_CGU1_VCO_OUT 8
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#define ADSP_SC58X_CLK_CGU1_PLLCLK 9
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#define ADSP_SC58X_CLK_CGU0_CDIV 10
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#define ADSP_SC58X_CLK_CGU0_SYSCLK 11
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#define ADSP_SC58X_CLK_CGU0_DDIV 12
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#define ADSP_SC58X_CLK_CGU0_ODIV 13
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#define ADSP_SC58X_CLK_CGU0_S0SELDIV 14
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#define ADSP_SC58X_CLK_CGU0_S1SELDIV 15
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#define ADSP_SC58X_CLK_CGU1_CDIV 16
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#define ADSP_SC58X_CLK_CGU1_SYSCLK 17
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#define ADSP_SC58X_CLK_CGU1_DDIV 18
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#define ADSP_SC58X_CLK_CGU1_ODIV 19
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#define ADSP_SC58X_CLK_CGU1_S0SELDIV 20
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#define ADSP_SC58X_CLK_CGU1_S1SELDIV 21
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#define ADSP_SC58X_CLK_CGU0_CCLK0 22
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#define ADSP_SC58X_CLK_CGU0_CCLK1 23
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#define ADSP_SC58X_CLK_CGU0_OCLK 24
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#define ADSP_SC58X_CLK_CGU0_DCLK 25
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#define ADSP_SC58X_CLK_CGU0_SCLK1 26
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#define ADSP_SC58X_CLK_CGU0_SCLK0 27
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#define ADSP_SC58X_CLK_CGU1_CCLK0 28
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#define ADSP_SC58X_CLK_CGU1_CCLK1 29
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#define ADSP_SC58X_CLK_CGU1_OCLK 30
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#define ADSP_SC58X_CLK_CGU1_DCLK 31
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#define ADSP_SC58X_CLK_CGU1_SCLK1 32
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#define ADSP_SC58X_CLK_CGU1_SCLK0 33
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#define ADSP_SC58X_CLK_OCLK0_HALF 34
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#define ADSP_SC58X_CLK_CCLK1_1_HALF 35
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#define ADSP_SC58X_CLK_SHARC0_SEL 36
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#define ADSP_SC58X_CLK_SHARC1_SEL 37
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#define ADSP_SC58X_CLK_ARM_SEL 38
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#define ADSP_SC58X_CLK_CDU_DDR_SEL 39
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#define ADSP_SC58X_CLK_CAN_SEL 40
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#define ADSP_SC58X_CLK_SPDIF_SEL 41
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#define ADSP_SC58X_CLK_RESERVED_SEL 42
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#define ADSP_SC58X_CLK_GIGE_SEL 43
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#define ADSP_SC58X_CLK_LP_SEL 44
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#define ADSP_SC58X_CLK_SDIO_SEL 45
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#define ADSP_SC58X_CLK_SHARC0 46
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#define ADSP_SC58X_CLK_SHARC1 47
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#define ADSP_SC58X_CLK_ARM 48
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#define ADSP_SC58X_CLK_CDU_DDR 49
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#define ADSP_SC58X_CLK_CAN 50
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#define ADSP_SC58X_CLK_SPDIF 51
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#define ADSP_SC58X_CLK_RESERVED 52
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#define ADSP_SC58X_CLK_GIGE 53
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#define ADSP_SC58X_CLK_LP 54
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#define ADSP_SC58X_CLK_SDIO 55
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#define ADSP_SC58X_CLK_END 56
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//ADSP-SC57X
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#define ADSP_SC57X_CLK_DUMMY 0
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#define ADSP_SC57X_CLK_SYS_CLKIN0 1
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#define ADSP_SC57X_CLK_SYS_CLKIN1 2
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#define ADSP_SC57X_CLK_CGU0_PLL_IN 3
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#define ADSP_SC57X_CLK_CGU0_PLLCLK 4
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#define ADSP_SC57X_CLK_CGU1_IN 5
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#define ADSP_SC57X_CLK_CGU1_PLL_IN 6
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#define ADSP_SC57X_CLK_CGU1_PLLCLK 7
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#define ADSP_SC57X_CLK_CGU0_CDIV 8
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#define ADSP_SC57X_CLK_CGU0_SYSCLK 9
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#define ADSP_SC57X_CLK_CGU0_DDIV 10
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#define ADSP_SC57X_CLK_CGU0_ODIV 11
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#define ADSP_SC57X_CLK_CGU0_S0SELDIV 12
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#define ADSP_SC57X_CLK_CGU0_S1SELDIV 13
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#define ADSP_SC57X_CLK_CGU1_CDIV 14
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#define ADSP_SC57X_CLK_CGU1_SYSCLK 15
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#define ADSP_SC57X_CLK_CGU1_DDIV 16
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#define ADSP_SC57X_CLK_CGU1_ODIV 17
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#define ADSP_SC57X_CLK_CGU1_S0SELDIV 18
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#define ADSP_SC57X_CLK_CGU1_S1SELDIV 19
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#define ADSP_SC57X_CLK_CGU0_CCLK0 20
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#define ADSP_SC57X_CLK_CGU0_CCLK1 21
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#define ADSP_SC57X_CLK_CGU0_OCLK 22
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#define ADSP_SC57X_CLK_CGU0_DCLK 23
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#define ADSP_SC57X_CLK_CGU0_SCLK1 24
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#define ADSP_SC57X_CLK_CGU0_SCLK0 25
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#define ADSP_SC57X_CLK_CGU1_CCLK0 26
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#define ADSP_SC57X_CLK_CGU1_CCLK1 27
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#define ADSP_SC57X_CLK_CGU1_OCLK 28
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#define ADSP_SC57X_CLK_CGU1_DCLK 29
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#define ADSP_SC57X_CLK_CGU1_SCLK1 30
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#define ADSP_SC57X_CLK_CGU1_SCLK0 31
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#define ADSP_SC57X_CLK_OCLK0_HALF 32
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#define ADSP_SC57X_CLK_CCLK1_1_HALF 33
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#define ADSP_SC57X_CLK_SHARC0_SEL 34
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#define ADSP_SC57X_CLK_SHARC1_SEL 35
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#define ADSP_SC57X_CLK_ARM_SEL 36
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#define ADSP_SC57X_CLK_CDU_DDR_SEL 37
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#define ADSP_SC57X_CLK_CAN_SEL 38
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#define ADSP_SC57X_CLK_SPDIF_SEL 39
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#define ADSP_SC57X_CLK_GIGE_SEL 40
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#define ADSP_SC57X_CLK_SDIO_SEL 41
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#define ADSP_SC57X_CLK_SHARC0 42
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#define ADSP_SC57X_CLK_SHARC1 43
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#define ADSP_SC57X_CLK_ARM 44
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#define ADSP_SC57X_CLK_CDU_DDR 45
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#define ADSP_SC57X_CLK_CAN 46
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#define ADSP_SC57X_CLK_SPDIF 47
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#define ADSP_SC57X_CLK_GIGE 48
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#define ADSP_SC57X_CLK_SDIO 49
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#define ADSP_SC57X_CLK_END 50
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#endif
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