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c3dc39a2f8
It is bad practice to include common.h in other header files since it can bring in any number of superfluous definitions. It implies that some C files don't include it and thus may be missing CONFIG options that are set up by that file. The C files should include these themselves. Update some header files in arch/arm to drop this. Signed-off-by: Simon Glass <sjg@chromium.org>
372 lines
8.5 KiB
C
372 lines
8.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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*/
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#ifndef _ASM_ARCH_PCC_H
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#define _ASM_ARCH_PCC_H
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#include <asm/arch/scg.h>
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/* PCC2 */
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enum pcc2_entry {
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/* On-Platform (32 entries) */
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RSVD0_PCC2_SLOT = 0,
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RSVD1_PCC2_SLOT = 1,
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CA7_GIC_PCC2_SLOT = 2,
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RSVD3_PCC2_SLOT = 3,
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RSVD4_PCC2_SLOT = 4,
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RSVD5_PCC2_SLOT = 5,
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RSVD6_PCC2_SLOT = 6,
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RSVD7_PCC2_SLOT = 7,
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DMA1_PCC2_SLOT = 8,
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RSVD9_PCC2_SLOT = 9,
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RSVD10_PCC2_SLOT = 10,
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RSVD11_PCC2_SLOT = 11,
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RSVD12_PCC2_SLOT = 12,
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RSVD13_PCC2_SLOT = 13,
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RSVD14_PCC2_SLOT = 14,
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RGPIO1_PCC2_SLOT = 15,
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FLEXBUS0_PCC2_SLOT = 16,
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RSVD17_PCC2_SLOT = 17,
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RSVD18_PCC2_SLOT = 18,
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RSVD19_PCC2_SLOT = 19,
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RSVD20_PCC2_SLOT = 20,
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RSVD21_PCC2_SLOT = 21,
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RSVD22_PCC2_SLOT = 22,
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RSVD23_PCC2_SLOT = 23,
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RSVD24_PCC2_SLOT = 24,
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RSVD25_PCC2_SLOT = 25,
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RSVD26_PCC2_SLOT = 26,
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SEMA42_1_PCC2_SLOT = 27,
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RSVD28_PCC2_SLOT = 28,
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RSVD29_PCC2_SLOT = 29,
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RSVD30_PCC2_SLOT = 30,
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RSVD31_PCC2_SLOT = 31,
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/* Off-Platform (96 entries) */
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RSVD32_PCC2_SLOT = 32,
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DMA1_CH_MUX0_PCC2_SLOT = 33,
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MU_B_PCC2_SLOT = 34,
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SNVS_PCC2_SLOT = 35,
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CAAM_PCC2_SLOT = 36,
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LPTPM4_PCC2_SLOT = 37,
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LPTPM5_PCC2_SLOT = 38,
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LPIT1_PCC2_SLOT = 39,
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RSVD40_PCC2_SLOT = 40,
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LPSPI2_PCC2_SLOT = 41,
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LPSPI3_PCC2_SLOT = 42,
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LPI2C4_PCC2_SLOT = 43,
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LPI2C5_PCC2_SLOT = 44,
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LPUART4_PCC2_SLOT = 45,
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LPUART5_PCC2_SLOT = 46,
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RSVD47_PCC2_SLOT = 47,
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RSVD48_PCC2_SLOT = 48,
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FLEXIO1_PCC2_SLOT = 49,
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RSVD50_PCC2_SLOT = 50,
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USBOTG0_PCC2_SLOT = 51,
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USBOTG1_PCC2_SLOT = 52,
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USBPHY_PCC2_SLOT = 53,
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USB_PL301_PCC2_SLOT = 54,
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USDHC0_PCC2_SLOT = 55,
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USDHC1_PCC2_SLOT = 56,
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RSVD57_PCC2_SLOT = 57,
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TRGMUX1_PCC2_SLOT = 58,
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RSVD59_PCC2_SLOT = 59,
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RSVD60_PCC2_SLOT = 60,
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WDG1_PCC2_SLOT = 61,
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SCG1_PCC2_SLOT = 62,
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PCC2_PCC2_SLOT = 63,
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PMC1_PCC2_SLOT = 64,
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SMC1_PCC2_SLOT = 65,
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RCM1_PCC2_SLOT = 66,
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WDG2_PCC2_SLOT = 67,
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RSVD68_PCC2_SLOT = 68,
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TEST_SPACE1_PCC2_SLOT = 69,
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TEST_SPACE2_PCC2_SLOT = 70,
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TEST_SPACE3_PCC2_SLOT = 71,
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RSVD72_PCC2_SLOT = 72,
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RSVD73_PCC2_SLOT = 73,
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RSVD74_PCC2_SLOT = 74,
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RSVD75_PCC2_SLOT = 75,
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RSVD76_PCC2_SLOT = 76,
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RSVD77_PCC2_SLOT = 77,
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RSVD78_PCC2_SLOT = 78,
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RSVD79_PCC2_SLOT = 79,
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RSVD80_PCC2_SLOT = 80,
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RSVD81_PCC2_SLOT = 81,
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RSVD82_PCC2_SLOT = 82,
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RSVD83_PCC2_SLOT = 83,
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RSVD84_PCC2_SLOT = 84,
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RSVD85_PCC2_SLOT = 85,
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RSVD86_PCC2_SLOT = 86,
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RSVD87_PCC2_SLOT = 87,
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RSVD88_PCC2_SLOT = 88,
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RSVD89_PCC2_SLOT = 89,
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RSVD90_PCC2_SLOT = 90,
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RSVD91_PCC2_SLOT = 91,
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RSVD92_PCC2_SLOT = 92,
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RSVD93_PCC2_SLOT = 93,
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RSVD94_PCC2_SLOT = 94,
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RSVD95_PCC2_SLOT = 95,
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RSVD96_PCC2_SLOT = 96,
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RSVD97_PCC2_SLOT = 97,
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RSVD98_PCC2_SLOT = 98,
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RSVD99_PCC2_SLOT = 99,
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RSVD100_PCC2_SLOT = 100,
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RSVD101_PCC2_SLOT = 101,
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RSVD102_PCC2_SLOT = 102,
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RSVD103_PCC2_SLOT = 103,
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RSVD104_PCC2_SLOT = 104,
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RSVD105_PCC2_SLOT = 105,
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RSVD106_PCC2_SLOT = 106,
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RSVD107_PCC2_SLOT = 107,
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RSVD108_PCC2_SLOT = 108,
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RSVD109_PCC2_SLOT = 109,
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RSVD110_PCC2_SLOT = 110,
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RSVD111_PCC2_SLOT = 111,
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RSVD112_PCC2_SLOT = 112,
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RSVD113_PCC2_SLOT = 113,
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RSVD114_PCC2_SLOT = 114,
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RSVD115_PCC2_SLOT = 115,
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RSVD116_PCC2_SLOT = 116,
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RSVD117_PCC2_SLOT = 117,
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RSVD118_PCC2_SLOT = 118,
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RSVD119_PCC2_SLOT = 119,
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RSVD120_PCC2_SLOT = 120,
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RSVD121_PCC2_SLOT = 121,
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RSVD122_PCC2_SLOT = 122,
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RSVD123_PCC2_SLOT = 123,
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RSVD124_PCC2_SLOT = 124,
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RSVD125_PCC2_SLOT = 125,
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RSVD126_PCC2_SLOT = 126,
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RSVD127_PCC2_SLOT = 127,
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};
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enum pcc3_entry {
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/* On-Platform (32 entries) */
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RSVD0_PCC3_SLOT = 0,
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RSVD1_PCC3_SLOT = 1,
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RSVD2_PCC3_SLOT = 2,
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RSVD3_PCC3_SLOT = 3,
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RSVD4_PCC3_SLOT = 4,
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RSVD5_PCC3_SLOT = 5,
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RSVD6_PCC3_SLOT = 6,
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RSVD7_PCC3_SLOT = 7,
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RSVD8_PCC3_SLOT = 8,
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RSVD9_PCC3_SLOT = 9,
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RSVD10_PCC3_SLOT = 10,
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RSVD11_PCC3_SLOT = 11,
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RSVD12_PCC3_SLOT = 12,
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RSVD13_PCC3_SLOT = 13,
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RSVD14_PCC3_SLOT = 14,
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RSVD15_PCC3_SLOT = 15,
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ROMCP1_PCC3_SLOT = 16,
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RSVD17_PCC3_SLOT = 17,
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RSVD18_PCC3_SLOT = 18,
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RSVD19_PCC3_SLOT = 19,
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RSVD20_PCC3_SLOT = 20,
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RSVD21_PCC3_SLOT = 21,
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RSVD22_PCC3_SLOT = 22,
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RSVD23_PCC3_SLOT = 23,
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RSVD24_PCC3_SLOT = 24,
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RSVD25_PCC3_SLOT = 25,
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RSVD26_PCC3_SLOT = 26,
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RSVD27_PCC3_SLOT = 27,
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RSVD28_PCC3_SLOT = 28,
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RSVD29_PCC3_SLOT = 29,
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RSVD30_PCC3_SLOT = 30,
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RSVD31_PCC3_SLOT = 31,
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/* Off-Platform (96 entries) */
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RSVD32_PCC3_SLOT = 32,
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LPTPM6_PCC3_SLOT = 33,
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LPTPM7_PCC3_SLOT = 34,
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RSVD35_PCC3_SLOT = 35,
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LPI2C6_PCC3_SLOT = 36,
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LPI2C7_PCC3_SLOT = 37,
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LPUART6_PCC3_SLOT = 38,
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LPUART7_PCC3_SLOT = 39,
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VIU0_PCC3_SLOT = 40,
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DSI0_PCC3_SLOT = 41,
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LCDIF0_PCC3_SLOT = 42,
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MMDC0_PCC3_SLOT = 43,
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IOMUXC1_PCC3_SLOT = 44,
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IOMUXC_DDR_PCC3_SLOT = 45,
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PORTC_PCC3_SLOT = 46,
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PORTD_PCC3_SLOT = 47,
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PORTE_PCC3_SLOT = 48,
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PORTF_PCC3_SLOT = 49,
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RSVD50_PCC3_SLOT = 50,
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PCC3_PCC3_SLOT = 51,
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RSVD52_PCC3_SLOT = 52,
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WKPU_PCC3_SLOT = 53,
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RSVD54_PCC3_SLOT = 54,
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RSVD55_PCC3_SLOT = 55,
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RSVD56_PCC3_SLOT = 56,
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RSVD57_PCC3_SLOT = 57,
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RSVD58_PCC3_SLOT = 58,
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RSVD59_PCC3_SLOT = 59,
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RSVD60_PCC3_SLOT = 60,
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RSVD61_PCC3_SLOT = 61,
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RSVD62_PCC3_SLOT = 62,
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RSVD63_PCC3_SLOT = 63,
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RSVD64_PCC3_SLOT = 64,
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RSVD65_PCC3_SLOT = 65,
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RSVD66_PCC3_SLOT = 66,
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RSVD67_PCC3_SLOT = 67,
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RSVD68_PCC3_SLOT = 68,
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RSVD69_PCC3_SLOT = 69,
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RSVD70_PCC3_SLOT = 70,
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RSVD71_PCC3_SLOT = 71,
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RSVD72_PCC3_SLOT = 72,
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RSVD73_PCC3_SLOT = 73,
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RSVD74_PCC3_SLOT = 74,
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RSVD75_PCC3_SLOT = 75,
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RSVD76_PCC3_SLOT = 76,
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RSVD77_PCC3_SLOT = 77,
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RSVD78_PCC3_SLOT = 78,
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RSVD79_PCC3_SLOT = 79,
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RSVD80_PCC3_SLOT = 80,
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GPU3D_PCC3_SLOT = 81,
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GPU2D_PCC3_SLOT = 82,
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RSVD83_PCC3_SLOT = 83,
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RSVD84_PCC3_SLOT = 84,
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RSVD85_PCC3_SLOT = 85,
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RSVD86_PCC3_SLOT = 86,
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RSVD87_PCC3_SLOT = 87,
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RSVD88_PCC3_SLOT = 88,
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RSVD89_PCC3_SLOT = 89,
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RSVD90_PCC3_SLOT = 90,
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RSVD91_PCC3_SLOT = 91,
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RSVD92_PCC3_SLOT = 92,
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RSVD93_PCC3_SLOT = 93,
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RSVD94_PCC3_SLOT = 94,
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RSVD95_PCC3_SLOT = 95,
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RSVD96_PCC3_SLOT = 96,
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RSVD97_PCC3_SLOT = 97,
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RSVD98_PCC3_SLOT = 98,
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RSVD99_PCC3_SLOT = 99,
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RSVD100_PCC3_SLOT = 100,
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RSVD101_PCC3_SLOT = 101,
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RSVD102_PCC3_SLOT = 102,
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RSVD103_PCC3_SLOT = 103,
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RSVD104_PCC3_SLOT = 104,
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RSVD105_PCC3_SLOT = 105,
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RSVD106_PCC3_SLOT = 106,
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RSVD107_PCC3_SLOT = 107,
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RSVD108_PCC3_SLOT = 108,
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RSVD109_PCC3_SLOT = 109,
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RSVD110_PCC3_SLOT = 110,
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RSVD111_PCC3_SLOT = 111,
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RSVD112_PCC3_SLOT = 112,
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RSVD113_PCC3_SLOT = 113,
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RSVD114_PCC3_SLOT = 114,
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RSVD115_PCC3_SLOT = 115,
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RSVD116_PCC3_SLOT = 116,
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RSVD117_PCC3_SLOT = 117,
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RSVD118_PCC3_SLOT = 118,
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RSVD119_PCC3_SLOT = 119,
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RSVD120_PCC3_SLOT = 120,
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RSVD121_PCC3_SLOT = 121,
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RSVD122_PCC3_SLOT = 122,
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RSVD123_PCC3_SLOT = 123,
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RSVD124_PCC3_SLOT = 124,
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RSVD125_PCC3_SLOT = 125,
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RSVD126_PCC3_SLOT = 126,
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RSVD127_PCC3_SLOT = 127,
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};
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/* PCC registers */
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#define PCC_PR_OFFSET 31
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#define PCC_PR_MASK (0x1 << PCC_PR_OFFSET)
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#define PCC_CGC_OFFSET 30
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#define PCC_CGC_MASK (0x1 << PCC_CGC_OFFSET)
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#define PCC_INUSE_OFFSET 29
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#define PCC_INUSE_MASK (0x1 << PCC_INUSE_OFFSET)
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#define PCC_PCS_OFFSET 24
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#define PCC_PCS_MASK (0x7 << PCC_PCS_OFFSET)
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#define PCC_FRAC_OFFSET 3
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#define PCC_FRAC_MASK (0x1 << PCC_FRAC_OFFSET)
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#define PCC_PCD_OFFSET 0
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#define PCC_PCD_MASK (0x7 << PCC_PCD_OFFSET)
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enum pcc_clksrc_type {
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CLKSRC_PER_PLAT = 0,
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CLKSRC_PER_BUS = 1,
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CLKSRC_NO_PCS = 2,
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};
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enum pcc_div_type {
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PCC_HAS_DIV,
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PCC_NO_DIV,
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};
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/* All peripheral clocks on A7 PCCs */
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enum pcc_clk {
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/*PCC2 clocks*/
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PER_CLK_DMA1 = 0,
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PER_CLK_RGPIO2P1,
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PER_CLK_FLEXBUS,
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PER_CLK_SEMA42_1,
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PER_CLK_DMA_MUX1,
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PER_CLK_SNVS,
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PER_CLK_CAAM,
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PER_CLK_LPTPM4,
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PER_CLK_LPTPM5,
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PER_CLK_LPIT1,
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PER_CLK_LPSPI2,
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PER_CLK_LPSPI3,
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PER_CLK_LPI2C4,
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PER_CLK_LPI2C5,
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PER_CLK_LPUART4,
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PER_CLK_LPUART5,
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PER_CLK_FLEXIO1,
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PER_CLK_USB0,
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PER_CLK_USB1,
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PER_CLK_USB_PHY,
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PER_CLK_USB_PL301,
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PER_CLK_USDHC0,
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PER_CLK_USDHC1,
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PER_CLK_WDG1,
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PER_CLK_WDG2,
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/*PCC3 clocks*/
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PER_CLK_LPTPM6,
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PER_CLK_LPTPM7,
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PER_CLK_LPI2C6,
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PER_CLK_LPI2C7,
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PER_CLK_LPUART6,
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PER_CLK_LPUART7,
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PER_CLK_VIU,
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PER_CLK_DSI,
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PER_CLK_LCDIF,
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PER_CLK_MMDC,
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PER_CLK_PCTLC,
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PER_CLK_PCTLD,
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PER_CLK_PCTLE,
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PER_CLK_PCTLF,
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PER_CLK_GPU3D,
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PER_CLK_GPU2D,
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};
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/* This structure keeps info for each pcc slot */
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struct pcc_entry {
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u32 pcc_base;
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u32 pcc_slot;
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enum pcc_clksrc_type clksrc;
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enum pcc_div_type div;
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};
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int pcc_clock_enable(enum pcc_clk clk, bool enable);
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int pcc_clock_sel(enum pcc_clk clk, enum scg_clk src);
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int pcc_clock_div_config(enum pcc_clk clk, bool frac, u8 div);
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bool pcc_clock_is_enable(enum pcc_clk clk);
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int pcc_clock_get_clksrc(enum pcc_clk clk, enum scg_clk *src);
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u32 pcc_clock_get_rate(enum pcc_clk clk);
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#endif
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