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4bc0104c97
This patch adds support for MediaTek MT7621 SoC. All files are dedicated for u-boot. The default build target is u-boot-mt7621.bin. The specification of this chip: https://www.mediatek.com/products/homenetworking/mt7621 Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
154 lines
5.0 KiB
C
154 lines
5.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2022 MediaTek Inc. All rights reserved.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#include <vsprintf.h>
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#include <asm/io.h>
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#include <asm/sections.h>
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#include <asm/byteorder.h>
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#include <asm/addrspace.h>
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#include <linux/string.h>
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#include "../mt7621.h"
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#include "dram.h"
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static const u32 ddr2_act[DDR_PARAM_SIZE] = {
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#if defined(CONFIG_MT7621_DRAM_DDR2_512M)
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0xAA00AA00, 0xAA00AA00, 0x00000007, 0x22174441,
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0x00000000, 0xF0748661, 0x40001273, 0x9F0A0481,
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0x0304692F, 0x15602842, 0x00008888, 0x88888888,
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0x00000000, 0x00000000, 0x00000000, 0x07100000,
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0x00001B63, 0x00002000, 0x00004000, 0x00006000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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#elif defined(CONFIG_MT7621_DRAM_DDR2_512M_W9751G6KB_A02_1066MHZ)
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0xAA00AA00, 0xAA00AA00, 0x00000007, 0x33484584,
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0x00000000, 0xF07486A1, 0x50001273, 0x9F010481,
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0x0304693F, 0x15602842, 0x00008888, 0x88888888,
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0x00000000, 0x00000000, 0x00000010, 0x07100000,
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0x00001F73, 0x00002000, 0x00004000, 0x00006000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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#elif defined(CONFIG_MT7621_DRAM_DDR2_1024M_W971GG6KB25_800MHZ)
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0xAA00AA00, 0xAA00AA00, 0x00000007, 0x22174430,
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0x01000000, 0xF0748661, 0x40001273, 0x9F0F0481,
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0x0304692F, 0x15602842, 0x00008888, 0x88888888,
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0x00000000, 0x00000000, 0x00000000, 0x07100000,
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0x00001B63, 0x00002000, 0x00004000, 0x00006000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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#elif defined(CONFIG_MT7621_DRAM_DDR2_1024M_W971GG6KB18_1066MHZ)
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0xAA00AA00, 0xAA00AA00, 0x00000007, 0x33484584,
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0x01000000, 0xF07486A1, 0x50001273, 0x9F070481,
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0x0304693F, 0x15602842, 0x00008888, 0x88888888,
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0x00000000, 0x00000000, 0x00000010, 0x07100000,
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0x00001F73, 0x00002000, 0x00004000, 0x00006000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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#else /* CONFIG_MT7621_DRAM_DDR2_1024M */
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0xAA00AA00, 0xAA00AA00, 0x00000007, 0x22174441,
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0x01000000, 0xF0748661, 0x40001273, 0x9F0F0481,
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0x0304692F, 0x15602842, 0x00008888, 0x88888888,
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0x00000000, 0x00000000, 0x00000000, 0x07100000,
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0x00001B63, 0x00002000, 0x00004000, 0x00006000,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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#endif
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};
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static const u32 ddr3_act[DDR_PARAM_SIZE] = {
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#if defined(CONFIG_MT7621_DRAM_DDR3_1024M)
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0xAA00AA00, 0xAA00AA00, 0x00000007, 0x44694683,
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0x01000000, 0xF07486A1, 0xC287221D, 0x9F060481,
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0x03046948, 0x15602842, 0x00008888, 0x88888888,
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0x00000000, 0x00000000, 0x00000210, 0x07100000,
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0x00001B61, 0x00002040, 0x00004010, 0x00006000,
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0x0C000000, 0x07070000, 0x00000000, 0x00000000,
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#elif defined(CONFIG_MT7621_DRAM_DDR3_4096M)
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0xAA00AA00, 0xAA00AA00, 0x00000007, 0x44694683,
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0x01000000, 0xF07486A1, 0xC287221D, 0x9F0F0481,
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0x03046948, 0x15602842, 0x00008888, 0x88888888,
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0x00000000, 0x00000000, 0x00000240, 0x07100000,
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0x00001B61, 0x00002040, 0x00004010, 0x00006000,
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0x0C000000, 0x07070000, 0x00000000, 0x00000000,
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#elif defined(CONFIG_MT7621_DRAM_DDR3_1024M_KGD)
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0xFF00FF00, 0xFF00FF00, 0x00000007, 0x44694683,
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0x01000000, 0xF07406A1, 0xC287221D, 0x9F060481,
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0x03046923, 0x152f2842, 0x00008888, 0x88888888,
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0x00000000, 0x00000000, 0x00000210, 0x07100000,
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0x00001B61, 0x00002040, 0x00004010, 0x00006000,
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0x0C000000, 0x07070000, 0x000C0000, 0x00000000,
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#else /* CONFIG_MT7621_DRAM_DDR3_2048M */
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0xAA00AA00, 0xAA00AA00, 0x00000007, 0x44694673,
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0x01000000, 0xF07486A1, 0xC287221D, 0x9F050481,
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0x03046948, 0x15602842, 0x00008888, 0x88888888,
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0x00000000, 0x00000000, 0x00000220, 0x07100000,
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0x00001B61, 0x00002040, 0x00004010, 0x00006000,
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0x0C000000, 0x07070000, 0x00000000, 0x00000000,
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#endif
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};
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#if defined(CONFIG_MT7621_DRAM_FREQ_400)
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#define DDR_FREQ_PARAM 0x41000000
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#elif defined(CONFIG_MT7621_DRAM_FREQ_1066)
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#define DDR_FREQ_PARAM 0x21000000
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#elif defined(CONFIG_MT7621_DRAM_FREQ_1200)
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#define DDR_FREQ_PARAM 0x11000000
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#else /* CONFIG_MT7621_DRAM_FREQ_800 */
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#define DDR_FREQ_PARAM 0x31000000
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#endif
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#define RG_MEPL_FBDIV_S 4
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#define RG_MEPL_FBDIV_M 0x7f
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static inline void word_copy(u32 *dest, const u32 *src, u32 count)
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{
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u32 i;
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for (i = 0; i < count; i++)
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dest[i] = src[i];
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}
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static u32 calc_cpu_pll_val(void)
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{
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u32 div, baseval, fb;
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div = get_xtal_mhz();
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if (div == 40) {
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div /= 2;
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baseval = 0xc0005802;
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} else {
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baseval = 0xc0004802;
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}
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fb = CONFIG_MT7621_CPU_FREQ / div - 1;
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if (fb > RG_MEPL_FBDIV_M)
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fb = RG_MEPL_FBDIV_M;
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return baseval | (fb << RG_MEPL_FBDIV_S);
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}
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void prepare_stage_bin(void)
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{
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u32 stage_size;
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const struct stage_header *stock_stage_bin =
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(const struct stage_header *)__image_copy_end;
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struct stage_header *new_stage_bin =
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(struct stage_header *)STAGE_LOAD_ADDR;
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if (be32_to_cpu(stock_stage_bin->ep) != STAGE_LOAD_ADDR)
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panic("Invalid DDR stage binary blob\n");
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stage_size = be32_to_cpu(stock_stage_bin->stage_size);
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word_copy((u32 *)new_stage_bin, (const u32 *)stock_stage_bin,
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(stage_size + sizeof(u32) - 1) / sizeof(u32));
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word_copy(new_stage_bin->ddr2_act, ddr2_act, DDR_PARAM_SIZE);
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word_copy(new_stage_bin->ddr3_act, ddr3_act, DDR_PARAM_SIZE);
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new_stage_bin->cpu_pll_cfg = calc_cpu_pll_val();
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new_stage_bin->ddr_pll_cfg = DDR_FREQ_PARAM;
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new_stage_bin->baudrate = CONFIG_BAUDRATE;
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}
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