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4bc0104c97
This patch adds support for MediaTek MT7621 SoC. All files are dedicated for u-boot. The default build target is u-boot-mt7621.bin. The specification of this chip: https://www.mediatek.com/products/homenetworking/mt7621 Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
340 lines
6.6 KiB
ArmAsm
340 lines
6.6 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2022 MediaTek Inc. All rights reserved.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#include <asm/cm.h>
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#include <asm/asm.h>
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#include <asm/regdef.h>
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#include <asm/cacheops.h>
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#include <asm/mipsregs.h>
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#include <asm/addrspace.h>
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#include <asm/mipsmtregs.h>
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#include "launch.h"
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.macro cache_loop curr, end, line_sz, op
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10: cache \op, 0(\curr)
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PTR_ADDU \curr, \curr, \line_sz
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bne \curr, \end, 10b
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.endm
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.set mt
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/*
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* Join the coherent domain
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* a0 = number of cores
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*/
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LEAF(join_coherent_domain)
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/*
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* Enable coherence and allow interventions from all other cores.
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* (Write access enabled via GCR_ACCESS by core 0.)
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*/
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li t1, 1
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sll t1, a0
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addiu t1, -1
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li t0, KSEG1ADDR(CONFIG_MIPS_CM_BASE)
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sw t1, GCR_Cx_COHERENCE(t0)
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ehb
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move t2, zero
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_next_coherent_core:
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sll t1, t2, GCR_Cx_OTHER_CORENUM_SHIFT
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sw t1, GCR_Cx_OTHER(t0)
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_busy_wait_coherent_core:
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lw t1, GCR_CO_COHERENCE(t0)
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beqz t1, _busy_wait_coherent_core
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addiu t2, 1
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bne t2, a0, _next_coherent_core
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jr ra
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END(join_coherent_domain)
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/*
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* All VPEs other than VPE0 will go here.
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*/
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LEAF(launch_vpe_entry)
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mfc0 t0, CP0_EBASE
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and t0, t0, MIPS_EBASE_CPUNUM
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/* per-VPE cpulaunch_t */
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li a0, KSEG0ADDR(CPULAUNCH)
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sll t1, t0, LOG2CPULAUNCH
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addu a0, t1
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/* Set CPU online flag */
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li t0, LAUNCH_FREADY
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sw t0, LAUNCH_FLAGS(a0)
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/* Enable count interrupt in mask, but do not enable interrupts */
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mfc0 t0, CP0_STATUS
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ori t0, STATUSF_IP7
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mtc0 t0, CP0_STATUS
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/* VPEs executing in wait code do not need a stack */
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li t9, KSEG0ADDR(LAUNCH_WAITCODE)
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jr t9
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END(launch_vpe_entry)
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/*
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* This function will not be executed in place.
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* It will be copied into memory, and VPEs other than VPE0 will be
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* started to run into this in-memory function.
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*/
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LEAF(launch_wait_code)
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.globl launch_wait_code_start
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launch_wait_code_start:
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move t0, a0
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start_poll:
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/* Poll CPU go flag */
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mtc0 zero, CP0_COUNT
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li t1, LAUNCHPERIOD
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mtc0 t1, CP0_COMPARE
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time_wait:
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/* Software wait */
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mfc0 t2, CP0_COUNT
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subu t2, t1
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bltz t2, time_wait
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/* Check the launch flag */
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lw t3, LAUNCH_FLAGS(t0)
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and t3, LAUNCH_FGO
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beqz t3, start_poll
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/* Reset the counter and interrupts to give naive clients a chance */
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mfc0 t1, CP0_STATUS
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ins t1, zero, STATUSB_IP7, 1
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mtc0 t1, CP0_STATUS
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mfc0 t1, CP0_COUNT
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subu t1, 1
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mtc0 t1, CP0_COMPARE
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/* Jump to kernel */
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lw t9, LAUNCH_PC(t0)
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lw gp, LAUNCH_GP(t0)
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lw sp, LAUNCH_SP(t0)
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lw a0, LAUNCH_A0(t0)
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move a1, zero
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move a2, zero
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move a3, zero
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ori t3, LAUNCH_FGONE
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sw t3, LAUNCH_FLAGS(t0)
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jr t9
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.globl launch_wait_code_end
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launch_wait_code_end:
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END(launch_wait_code)
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/*
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* Core1 will go here.
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*/
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LEAF(launch_core_entry)
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/* Disable caches */
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bal mips_cache_disable
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/* Initialize L1 cache only */
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li a0, CONFIG_SYS_ICACHE_SIZE
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li a1, CONFIG_SYS_ICACHE_LINE_SIZE
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li a2, CONFIG_SYS_DCACHE_SIZE
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li a3, CONFIG_SYS_DCACHE_LINE_SIZE
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mtc0 zero, CP0_TAGLO
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mtc0 zero, CP0_TAGLO, 2
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ehb
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/*
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* Initialize the I-cache first,
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*/
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li t0, KSEG0
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addu t1, t0, a0
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/* clear tag to invalidate */
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cache_loop t0, t1, a1, INDEX_STORE_TAG_I
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#ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
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/* fill once, so data field parity is correct */
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PTR_LI t0, KSEG0
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cache_loop t0, t1, a1, FILL
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/* invalidate again - prudent but not strictly necessary */
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PTR_LI t0, KSEG0
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cache_loop t0, t1, a1, INDEX_STORE_TAG_I
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#endif
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/*
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* then initialize D-cache.
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*/
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PTR_LI t0, KSEG0
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PTR_ADDU t1, t0, a2
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/* clear all tags */
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cache_loop t0, t1, a3, INDEX_STORE_TAG_D
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#ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
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/* load from each line (in cached space) */
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PTR_LI t0, KSEG0
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2: LONG_L zero, 0(t0)
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PTR_ADDU t0, a3
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bne t0, t1, 2b
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/* clear all tags */
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PTR_LI t0, KSEG0
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cache_loop t0, t1, a3, INDEX_STORE_TAG_D
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#endif
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/* Set Cache Mode */
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mfc0 t0, CP0_CONFIG
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li t1, CONF_CM_CACHABLE_COW
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ins t0, t1, 0, 3
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mtc0 t0, CP0_CONFIG
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/* Join the coherent domain */
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li a0, 2
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bal join_coherent_domain
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/* Bootup Core0/VPE1 */
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bal boot_vpe1
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b launch_vpe_entry
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END(launch_core_entry)
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/*
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* Bootup VPE1.
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* This subroutine must be executed from VPE0 with VPECONF0[MVP] already set.
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*/
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LEAF(boot_vpe1)
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mfc0 t0, CP0_MVPCONF0
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/* a0 = number of TCs - 1 */
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ext a0, t0, MVPCONF0_PTC_SHIFT, 8
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beqz a0, _vpe1_init_done
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/* a1 = number of VPEs - 1 */
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ext a1, t0, MVPCONF0_PVPE_SHIFT, 4
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beqz a1, _vpe1_init_done
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/* a2 = current TC No. */
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move a2, zero
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/* Enter VPE Configuration State */
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mfc0 t0, CP0_MVPCONTROL
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or t0, MVPCONTROL_VPC
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mtc0 t0, CP0_MVPCONTROL
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ehb
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_next_tc:
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/* Set the TC number to be used on MTTR and MFTR instructions */
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mfc0 t0, CP0_VPECONTROL
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ins t0, a2, 0, 8
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mtc0 t0, CP0_VPECONTROL
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ehb
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/* TC0 is already bound */
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beqz a2, _next_vpe
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/* Halt current TC */
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li t0, TCHALT_H
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mttc0 t0, CP0_TCHALT
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ehb
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/* If there is spare TC, bind it to the last VPE (VPE[a1]) */
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slt t1, a1, a2
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bnez t1, _vpe_bind_tc
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move t1, a1
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/* Set Exclusive TC for active TC */
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mftc0 t0, CP0_VPECONF0
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ins t0, a2, VPECONF0_XTC_SHIFT, 8
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mttc0 t0, CP0_VPECONF0
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move t1, a2
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_vpe_bind_tc:
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/* Bind TC to a VPE */
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mftc0 t0, CP0_TCBIND
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ins t0, t1, TCBIND_CURVPE_SHIFT, 4
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mttc0 t0, CP0_TCBIND
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/*
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* Set up CP0_TCSTATUS register:
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* Disable Coprocessor Usable bits
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* Disable MDMX/DSP ASE
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* Clear Dirty TC
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* not dynamically allocatable
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* not allocated
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* Kernel mode
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* interrupt exempt
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* ASID 0
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*/
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li t0, TCSTATUS_IXMT
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mttc0 t0, CP0_TCSTATUS
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_next_vpe:
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slt t1, a1, a2
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bnez t1, _done_vpe # No more VPEs
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/* Disable TC multi-threading */
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mftc0 t0, CP0_VPECONTROL
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ins t0, zero, VPECONTROL_TE_SHIFT, 1
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mttc0 t0, CP0_VPECONTROL
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/* Skip following configuration for TC0 */
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beqz a2, _done_vpe
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/* Deactivate VPE, set Master VPE */
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mftc0 t0, CP0_VPECONF0
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ins t0, zero, VPECONF0_VPA_SHIFT, 1
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or t0, VPECONF0_MVP
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mttc0 t0, CP0_VPECONF0
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mfc0 t0, CP0_STATUS
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mttc0 t0, CP0_STATUS
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mttc0 zero, CP0_EPC
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mttc0 zero, CP0_CAUSE
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mfc0 t0, CP0_CONFIG
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mttc0 t0, CP0_CONFIG
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/*
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* VPE1 of each core can execute cached as its L1 I$ has already
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* been initialized.
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* and the L2$ has been initialized or "disabled" via CCA override.
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*/
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PTR_LA t0, _start
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mttc0 t0, CP0_TCRESTART
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/* Unset Interrupt Exempt, set Activate Thread */
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mftc0 t0, CP0_TCSTATUS
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ins t0, zero, TCSTATUS_IXMT_SHIFT, 1
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ori t0, TCSTATUS_A
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mttc0 t0, CP0_TCSTATUS
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/* Resume TC */
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mttc0 zero, CP0_TCHALT
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/* Activate VPE */
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mftc0 t0, CP0_VPECONF0
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ori t0, VPECONF0_VPA
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mttc0 t0, CP0_VPECONF0
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_done_vpe:
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addu a2, 1
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sltu t0, a0, a2
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beqz t0, _next_tc
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mfc0 t0, CP0_MVPCONTROL
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/* Enable all activated VPE to execute */
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ori t0, MVPCONTROL_EVP
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/* Exit VPE Configuration State */
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ins t0, zero, MVPCONTROL_VPC_SHIFT, 1
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mtc0 t0, CP0_MVPCONTROL
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ehb
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_vpe1_init_done:
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jr ra
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END(boot_vpe1)
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