mirror of
https://github.com/smaeul/u-boot.git
synced 2025-11-03 21:48:15 +00:00
e6a8c6f5c0
Add pe2201 platform code and the device tree of pe2201 platform board.
The initial support comprises the UART and PCIe.
Signed-off-by: TracyMg_Li <TracyMg_Li@outlook.com>
Changes since v1:
fix space corrupt.
Changes since v2:
switch to bootstd and text environment.
Changes since v3:
add environment variables.
191 lines
4.4 KiB
C
191 lines
4.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2023, Phytium Technology Co., Ltd.
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* lixinde <lixinde@phytium.com.cn>
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* weichangzheng <weichangzheng@phytium.com.cn>
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*/
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#include <stdio.h>
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#include <linux/arm-smccc.h>
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#include <init.h>
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#include "cpu.h"
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struct ddr_spd {
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/***************** read from spd ******************/
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u8 dimm_type; /* 1: RDIMM; 2: UDIMM; 3: SODIMM; 4: LRDIMM */
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u8 data_width; /* 0: x4; 1: x8; 2: x16; 3: x32 */
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u8 mirror_type; /* 0: standard; 1: mirror */
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u8 ecc_type; /* 0: no-ecc; 1: ecc */
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u8 dram_type; /* 0xB: DDR3; 0xC: DDR4 */
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u8 rank_num;
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u8 row_num;
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u8 col_num;
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u8 bg_num; /* DDR4/DDR5 */
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u8 bank_num;
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u16 module_manufacturer_id;
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u16 taamin;
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u16 trcdmin;
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u16 trpmin;
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u16 trasmin;
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u16 trcmin;
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u16 tfawmin; /* only DDR3/DDR4 */
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u16 trrd_smin; /* only DDR4 */
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u16 trrd_lmin; /* only DDR4 */
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u16 tccd_lmin; /* only DDR4 */
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u16 twrmin;
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u16 twtr_smin; /* only DDR4 */
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u16 twtr_lmin; /* only DDR4 */
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u32 trfc1min;
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u32 trfc2min;
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u32 trfc4_rfcsbmin; /* DDR4: tRFC4min; DDR5: tRFCsbmin */
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u8 resv[8];
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/***************** RCD control words ******************/
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u8 f0rc03; /* bit[3:2]:CS bit[1:0]:CA */
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u8 f0rc04; /* bit[3:2]:ODT bit[1:0]:CKE */
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u8 f0rc05; /* bit[3:2]:CLK-A side bit[1:0]:CLK-B side */
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u8 rcd_num; /* Registers used on RDIMM */
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u8 lrdimm_resv[4];
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u8 lrdimm_resv1[8];
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u8 lrdimm_resv2[8];
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} __attribute((aligned(4)));
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struct mcu_config {
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u32 magic;
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u32 version;
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u32 size;
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u8 rev1[4];
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u8 ch_enable;
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u8 resv1[7];
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u64 misc_enable;
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u8 train_debug;
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u8 train_recover;
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u8 train_param_type;
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u8 train_param_1; /* DDR4: cpu_odt */
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u8 train_param_2; /* DDR4: cpu_drv */
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u8 train_param_3; /* DDR4: mr_drv */
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u8 train_param_4; /* DDR4: rtt_nom */
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u8 train_param_5; /* DDR4: rtt_park */
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u8 train_param_6; /* DDR4: rtt_wr */
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u8 resv2[7];
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/***************** for LPDDR4 dq swap ******************/
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u32 data_byte_swap;
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u32 slice0_dq_swizzle;
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u32 slice1_dq_swizzle;
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u32 slice2_dq_swizzle;
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u32 slice3_dq_swizzle;
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u32 slice4_dq_swizzle;
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u32 slice5_dq_swizzle;
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u32 slice6_dq_swizzle;
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u32 slice7_dq_swizzle;
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u8 resv3[4];
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u8 resv4[8];
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struct ddr_spd ddr_spd_info;
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} __attribute((aligned(4)));
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static void get_mcu_up_info_default(struct mcu_config *pm)
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{
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pm->magic = PARAMETER_MCU_MAGIC;
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pm->version = PARAM_MCU_VERSION;
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pm->size = PARAM_MCU_SIZE;
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pm->ch_enable = PARAM_CH_ENABLE;
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}
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static u8 init_dimm_param(struct mcu_config *pm)
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{
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debug("manual config dimm info...\n");
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pm->misc_enable = 0x2001;
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pm->train_debug = 0x0;
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pm->train_recover = 0x0;
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pm->train_param_type = 0x0;
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pm->train_param_1 = 0x0;
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pm->train_param_2 = 0x0;
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pm->train_param_3 = 0x0;
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pm->train_param_4 = 0x0;
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pm->train_param_5 = 0x0;
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pm->train_param_6 = 0x0;
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pm->data_byte_swap = 0x76543210;
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pm->slice0_dq_swizzle = 0x3145726;
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pm->slice1_dq_swizzle = 0x54176230;
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pm->slice2_dq_swizzle = 0x57604132;
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pm->slice3_dq_swizzle = 0x20631547;
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pm->slice4_dq_swizzle = 0x16057423;
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pm->slice5_dq_swizzle = 0x16057423;
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pm->slice6_dq_swizzle = 0x16057423;
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pm->slice7_dq_swizzle = 0x16057423;
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pm->ddr_spd_info.dimm_type = RDIMM_TYPE;
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pm->ddr_spd_info.data_width = DIMM_X16;
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pm->ddr_spd_info.mirror_type = NO_MIRROR;
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pm->ddr_spd_info.ecc_type = NO_ECC_TYPE;
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pm->ddr_spd_info.dram_type = LPDDR4_TYPE;
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pm->ddr_spd_info.rank_num = 0x1;
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pm->ddr_spd_info.row_num = 0x10;
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pm->ddr_spd_info.col_num = 0xa;
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pm->ddr_spd_info.bg_num = 0x0;
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pm->ddr_spd_info.bank_num = 0x8;
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pm->ddr_spd_info.taamin = 0x0;
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pm->ddr_spd_info.trcdmin = 0x0;
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pm->ddr_spd_info.trpmin = 0x0;
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pm->ddr_spd_info.trasmin = 0x0;
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pm->ddr_spd_info.trcmin = 0x0;
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pm->ddr_spd_info.tfawmin = 0x0;
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pm->ddr_spd_info.trrd_smin = 0x0;
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pm->ddr_spd_info.trrd_lmin = 0x0;
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pm->ddr_spd_info.tccd_lmin = 0x0;
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pm->ddr_spd_info.twrmin = 0x0;
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pm->ddr_spd_info.twtr_smin = 0x0;
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pm->ddr_spd_info.twtr_lmin = 0x0;
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return 0;
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}
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void get_default_mcu_info(u8 *data)
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{
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get_mcu_up_info_default((struct mcu_config *)data);
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}
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void fix_mcu_info(u8 *data)
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{
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struct mcu_config *mcu_info = (struct mcu_config *)data;
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init_dimm_param(mcu_info);
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}
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void ddr_init(void)
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{
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u8 buffer[0x100];
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struct arm_smccc_res res;
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get_default_mcu_info(buffer);
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fix_mcu_info(buffer);
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arm_smccc_smc(CPU_INIT_MEM, 0, (u64)buffer, 0, 0, 0, 0, 0, &res);
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if (res.a0 != 0)
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panic("DRAM init failed :0x%lx\n", res.a0);
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}
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