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164 lines
4.1 KiB
C
164 lines
4.1 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
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/*
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* Qualcomm MSM8996 interconnect IDs
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*
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* Copyright (c) 2021 Yassine Oudjana <y.oudjana@protonmail.com>
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*/
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#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8996_H
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#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8996_H
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/* A0NOC */
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#define MASTER_PCIE_0 0
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#define MASTER_PCIE_1 1
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#define MASTER_PCIE_2 2
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/* A1NOC */
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#define MASTER_CNOC_A1NOC 0
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#define MASTER_CRYPTO_CORE0 1
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#define MASTER_PNOC_A1NOC 2
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/* A2NOC */
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#define MASTER_USB3 0
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#define MASTER_IPA 1
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#define MASTER_UFS 2
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/* BIMC */
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#define MASTER_AMPSS_M0 0
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#define MASTER_GRAPHICS_3D 1
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#define MASTER_MNOC_BIMC 2
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#define MASTER_SNOC_BIMC 3
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#define SLAVE_EBI_CH0 4
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#define SLAVE_HMSS_L3 5
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#define SLAVE_BIMC_SNOC_0 6
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#define SLAVE_BIMC_SNOC_1 7
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/* CNOC */
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#define MASTER_SNOC_CNOC 0
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#define MASTER_QDSS_DAP 1
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#define SLAVE_CNOC_A1NOC 2
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#define SLAVE_CLK_CTL 3
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#define SLAVE_TCSR 4
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#define SLAVE_TLMM 5
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#define SLAVE_CRYPTO_0_CFG 6
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#define SLAVE_MPM 7
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#define SLAVE_PIMEM_CFG 8
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#define SLAVE_IMEM_CFG 9
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#define SLAVE_MESSAGE_RAM 10
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#define SLAVE_BIMC_CFG 11
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#define SLAVE_PMIC_ARB 12
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#define SLAVE_PRNG 13
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#define SLAVE_DCC_CFG 14
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#define SLAVE_RBCPR_MX 15
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#define SLAVE_QDSS_CFG 16
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#define SLAVE_RBCPR_CX 17
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#define SLAVE_QDSS_RBCPR_APU 18
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#define SLAVE_CNOC_MNOC_CFG 19
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#define SLAVE_SNOC_CFG 20
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#define SLAVE_SNOC_MPU_CFG 21
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#define SLAVE_EBI1_PHY_CFG 22
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#define SLAVE_A0NOC_CFG 23
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#define SLAVE_PCIE_1_CFG 24
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#define SLAVE_PCIE_2_CFG 25
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#define SLAVE_PCIE_0_CFG 26
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#define SLAVE_PCIE20_AHB2PHY 27
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#define SLAVE_A0NOC_MPU_CFG 28
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#define SLAVE_UFS_CFG 29
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#define SLAVE_A1NOC_CFG 30
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#define SLAVE_A1NOC_MPU_CFG 31
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#define SLAVE_A2NOC_CFG 32
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#define SLAVE_A2NOC_MPU_CFG 33
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#define SLAVE_SSC_CFG 34
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#define SLAVE_A0NOC_SMMU_CFG 35
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#define SLAVE_A1NOC_SMMU_CFG 36
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#define SLAVE_A2NOC_SMMU_CFG 37
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#define SLAVE_LPASS_SMMU_CFG 38
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#define SLAVE_CNOC_MNOC_MMSS_CFG 39
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/* MNOC */
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#define MASTER_CNOC_MNOC_CFG 0
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#define MASTER_CPP 1
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#define MASTER_JPEG 2
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#define MASTER_MDP_PORT0 3
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#define MASTER_MDP_PORT1 4
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#define MASTER_ROTATOR 5
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#define MASTER_VIDEO_P0 6
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#define MASTER_VFE 7
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#define MASTER_SNOC_VMEM 8
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#define MASTER_VIDEO_P0_OCMEM 9
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#define MASTER_CNOC_MNOC_MMSS_CFG 10
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#define SLAVE_MNOC_BIMC 11
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#define SLAVE_VMEM 12
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#define SLAVE_SERVICE_MNOC 13
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#define SLAVE_MMAGIC_CFG 14
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#define SLAVE_CPR_CFG 15
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#define SLAVE_MISC_CFG 16
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#define SLAVE_VENUS_THROTTLE_CFG 17
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#define SLAVE_VENUS_CFG 18
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#define SLAVE_VMEM_CFG 19
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#define SLAVE_DSA_CFG 20
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#define SLAVE_MMSS_CLK_CFG 21
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#define SLAVE_DSA_MPU_CFG 22
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#define SLAVE_MNOC_MPU_CFG 23
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#define SLAVE_DISPLAY_CFG 24
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#define SLAVE_DISPLAY_THROTTLE_CFG 25
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#define SLAVE_CAMERA_CFG 26
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#define SLAVE_CAMERA_THROTTLE_CFG 27
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#define SLAVE_GRAPHICS_3D_CFG 28
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#define SLAVE_SMMU_MDP_CFG 29
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#define SLAVE_SMMU_ROT_CFG 30
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#define SLAVE_SMMU_VENUS_CFG 31
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#define SLAVE_SMMU_CPP_CFG 32
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#define SLAVE_SMMU_JPEG_CFG 33
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#define SLAVE_SMMU_VFE_CFG 34
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/* PNOC */
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#define MASTER_SNOC_PNOC 0
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#define MASTER_SDCC_1 1
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#define MASTER_SDCC_2 2
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#define MASTER_SDCC_4 3
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#define MASTER_USB_HS 4
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#define MASTER_BLSP_1 5
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#define MASTER_BLSP_2 6
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#define MASTER_TSIF 7
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#define SLAVE_PNOC_A1NOC 8
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#define SLAVE_USB_HS 9
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#define SLAVE_SDCC_2 10
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#define SLAVE_SDCC_4 11
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#define SLAVE_TSIF 12
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#define SLAVE_BLSP_2 13
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#define SLAVE_SDCC_1 14
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#define SLAVE_BLSP_1 15
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#define SLAVE_PDM 16
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#define SLAVE_AHB2PHY 17
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/* SNOC */
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#define MASTER_HMSS 0
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#define MASTER_QDSS_BAM 1
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#define MASTER_SNOC_CFG 2
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#define MASTER_BIMC_SNOC_0 3
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#define MASTER_BIMC_SNOC_1 4
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#define MASTER_A0NOC_SNOC 5
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#define MASTER_A1NOC_SNOC 6
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#define MASTER_A2NOC_SNOC 7
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#define MASTER_QDSS_ETR 8
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#define SLAVE_A0NOC_SNOC 9
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#define SLAVE_A1NOC_SNOC 10
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#define SLAVE_A2NOC_SNOC 11
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#define SLAVE_HMSS 12
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#define SLAVE_LPASS 13
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#define SLAVE_USB3 14
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#define SLAVE_SNOC_BIMC 15
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#define SLAVE_SNOC_CNOC 16
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#define SLAVE_IMEM 17
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#define SLAVE_PIMEM 18
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#define SLAVE_SNOC_VMEM 19
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#define SLAVE_SNOC_PNOC 20
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#define SLAVE_QDSS_STM 21
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#define SLAVE_PCIE_0 22
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#define SLAVE_PCIE_1 23
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#define SLAVE_PCIE_2 24
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#define SLAVE_SERVICE_SNOC 25
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#endif
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