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The maximum supported peripheral clock frequency of the zynq depends on the IO routing. The MIO and EMIO support a maximum frequency of 50 MHz respectively 25 MHz. Use the max-frequency value of the device tree to determine the maximal supported peripheral clock frequency. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
115 lines
2.5 KiB
C
115 lines
2.5 KiB
C
/*
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* (C) Copyright 2013 - 2015 Xilinx, Inc.
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*
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* Xilinx Zynq SD Host Controller Interface
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <clk.h>
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#include <common.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <libfdt.h>
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#include <malloc.h>
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#include <sdhci.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifndef CONFIG_ZYNQ_SDHCI_MIN_FREQ
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# define CONFIG_ZYNQ_SDHCI_MIN_FREQ 0
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#endif
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struct arasan_sdhci_plat {
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struct mmc_config cfg;
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struct mmc mmc;
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unsigned int f_max;
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};
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static int arasan_sdhci_probe(struct udevice *dev)
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{
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struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
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struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
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struct sdhci_host *host = dev_get_priv(dev);
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struct clk clk;
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unsigned long clock;
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int ret;
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret < 0) {
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dev_err(dev, "failed to get clock\n");
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return ret;
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}
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clock = clk_get_rate(&clk);
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if (IS_ERR_VALUE(clock)) {
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dev_err(dev, "failed to get rate\n");
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return clock;
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}
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debug("%s: CLK %ld\n", __func__, clock);
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ret = clk_enable(&clk);
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if (ret && ret != -ENOSYS) {
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dev_err(dev, "failed to enable clock\n");
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return ret;
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}
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host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
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SDHCI_QUIRK_BROKEN_R1B;
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#ifdef CONFIG_ZYNQ_HISPD_BROKEN
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host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
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#endif
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host->max_clk = clock;
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ret = sdhci_setup_cfg(&plat->cfg, host, plat->f_max,
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CONFIG_ZYNQ_SDHCI_MIN_FREQ);
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host->mmc = &plat->mmc;
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if (ret)
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return ret;
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host->mmc->priv = host;
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host->mmc->dev = dev;
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upriv->mmc = host->mmc;
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return sdhci_probe(dev);
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}
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static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
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{
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struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
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struct sdhci_host *host = dev_get_priv(dev);
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host->name = dev->name;
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host->ioaddr = (void *)dev_get_addr(dev);
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plat->f_max = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
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"max-frequency", CONFIG_ZYNQ_SDHCI_MAX_FREQ);
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return 0;
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}
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static int arasan_sdhci_bind(struct udevice *dev)
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{
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struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
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return sdhci_bind(dev, &plat->mmc, &plat->cfg);
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}
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static const struct udevice_id arasan_sdhci_ids[] = {
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{ .compatible = "arasan,sdhci-8.9a" },
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{ }
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};
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U_BOOT_DRIVER(arasan_sdhci_drv) = {
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.name = "arasan_sdhci",
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.id = UCLASS_MMC,
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.of_match = arasan_sdhci_ids,
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.ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
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.ops = &sdhci_ops,
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.bind = arasan_sdhci_bind,
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.probe = arasan_sdhci_probe,
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.priv_auto_alloc_size = sizeof(struct sdhci_host),
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.platdata_auto_alloc_size = sizeof(struct arasan_sdhci_plat),
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};
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