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72e0a0e1c7
Add the "u-boot,dm-pre-reloc" property to the "ti,tilcdc,panel" compatible node. In this way the video-uclass module can allocate the amount of memory needed to be assigned to the frame buffer. For boards that support Linux the property is added to the *-u-boot.dtsi file since it is a u-boot specific dt flag. Ran building tests with CONFIG_AM335X_LCD enabled and disabled for the following configurations: - brxre1_defconfig --> success - am335x_guardian_defconfig --> success - am335x_evm_defconfig --> success - da850evm_defconfig --> failure with CONFIG_AM335X_LCD enabled Enabling CONFIG_AM335X_LCD in da850evm_defconfig causes building errors even without applying the patch. The driver has never been enabled on the da850 and must be adapted for this platform. Signed-off-by: Dario Binacchi <dariobin@libero.it> Tested-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Felix Brack <fb@ltec.ch>
366 lines
6.0 KiB
Plaintext
366 lines
6.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 B&R Industrial Automation GmbH
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* http://www.br-automation.com
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*
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*/
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/dts-v1/;
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#include "am33xx.dtsi"
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/ {
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model = "BRPPT1 (NAND) Panel";
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compatible = "ti,am33xx";
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fset: factory-settings {
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bl-version = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456890";
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version = <0x0100>;
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order-no = "6PPT30 (NAND)";
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hw-revision = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456890";
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serial-no = "0";
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device-id = <0x0>;
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parent-id = <0x0>;
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hw-variant = <0x1>;
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};
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aliases {
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ds1bkl0 = &pwmbacklight;
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ds1bkl1 = &tps_bl;
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ds1timing = &timing0;
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ds1ctrl = &lcdc;
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gpmc = &gpmc;
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mmc = &mmc2;
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fset = &fset;
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};
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chosen {
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bootargs = "console=ttyO0,115200 earlyprintk";
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stdout-path = &uart0;
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};
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memory {
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device_type = "memory";
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reg = <0x80000000 0x10000000>; /* 256 MB */
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};
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panel {
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status = "disabled";
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compatible = "ti,tilcdc,panel";
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enable-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
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backlight = <&pwmbacklight>;
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bkl-pwm = <&pwmbacklight>;
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bkl-tps = <&tps_bl>;
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u-boot,dm-pre-reloc;
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panel-info {
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ac-bias = <255>;
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ac-bias-intrpt = <0>;
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dma-burst-sz = <16>;
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bpp = <32>;
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fdd = <0x80>;
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sync-edge = <0>;
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sync-ctrl = <1>;
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raster-order = <0>;
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fifo-th = <0>;
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};
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display-timings {
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native-mode = <&timing0>;
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timing0: lcd {
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clock-frequency = <32000000>;
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hactive = <800>;
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vactive = <480>;
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hfront-porch = <2>;
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hback-porch = <192>;
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hsync-len = <1>;
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vfront-porch = <20>;
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vback-porch = <2>;
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vsync-len = <1>;
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hsync-active = <1>;
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vsync-active = <1>;
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pupdelay = <10>;
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pondelay = <10>;
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};
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};
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};
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vmmcsd_fixed: fixedregulator@0 {
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compatible = "regulator-fixed";
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regulator-name = "vmmcsd_fixed";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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pwm0: omap-pwm@timer5 {
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compatible = "ti,omap-dmtimer-pwm";
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ti,timers = <&timer5>;
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#pwm-cells = <3>;
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};
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pwm1: omap-pwm@timer6 {
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compatible = "ti,omap-dmtimer-pwm";
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ti,timers = <&timer6>;
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#pwm-cells = <3>;
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};
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beeper: pwm-beep {
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compatible = "pwm-beeper";
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pwms = <&pwm0 0 0 0>;
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};
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pwmbacklight: pwm-bkl {
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compatible = "pwm-backlight";
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pwms = <&pwm1 0 5000000 0>;
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default-brightness-level = <255>;
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brightness-levels = <0 16 32 64 128 170 202 234 255>;
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power-supply = <&vmmcsd_fixed>;
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enable-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
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};
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};
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&uart0 { /* console uart */
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u-boot,dm-spl;
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status = "okay";
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};
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&uart1 {
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status = "okay";
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};
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&i2c0 {
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u-boot,dm-spl;
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status = "okay";
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clock-frequency = <400000>;
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tps: tps@24 { /* PMIC controller */
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u-boot,dm-spl;
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reg = <0x24>;
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compatible = "ti,tps65217";
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tps_bl: backlight {
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compatible = "ti,tps65217-bl";
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isel = <1>; /* 1 - ISET1, 2 ISET2 */
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fdim = <1000>; /* TPS65217_BL_FDIM_1kHZ */
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default-brightness = <50>;
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};
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};
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};
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&i2c2 {
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status = "okay";
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clock-frequency = <100000>;
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};
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&edma {
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status = "okay";
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};
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&cppi41dma {
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status = "okay";
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};
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&usb {
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status = "okay";
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};
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&usb_ctrl_mod {
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status = "okay";
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};
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&usb0_phy {
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status = "okay";
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};
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&usb1_phy {
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status = "okay";
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};
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&usb0 {
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status = "okay";
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dr_mode = "host";
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};
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&usb1 {
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status = "okay";
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dr_mode = "host";
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};
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&davinci_mdio {
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status = "okay";
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phy0: ethernet-phy@0 {
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reg = <1>;
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};
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phy1: ethernet-phy@1 {
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reg = <2>;
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};
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};
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&mac {
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dual_emac;
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status = "okay";
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};
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&cpsw_emac0 {
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phy-handle = <&phy0>;
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dual_emac_res_vlan = <1>;
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phy-mode = "mii";
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};
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&cpsw_emac1 {
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phy-handle = <&phy1>;
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dual_emac_res_vlan = <2>;
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phy-mode = "mii";
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};
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&mmc2 {
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vmmc-supply = <&vmmcsd_fixed>;
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bus-width = <0x4>;
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ti,non-removable;
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ti,needs-special-hs-handling;
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ti,vcc-aux-disable-is-sleep;
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status = "disabled";
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};
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&lcdc {
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status = "disabled";
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};
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&elm {
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status = "okay";
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};
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&sham {
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status = "okay";
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};
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&aes {
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status = "okay";
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};
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&gpio0 {
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u-boot,dm-spl;
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ti,no-reset-on-init;
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};
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&gpio1 {
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u-boot,dm-spl;
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ti,no-reset-on-init;
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};
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&gpio2 {
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u-boot,dm-spl;
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ti,no-reset-on-init;
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};
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&gpio3 {
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u-boot,dm-spl;
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ti,no-reset-on-init;
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};
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&wdt2 {
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ti,no-reset-on-init;
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ti,no-idle-on-init;
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};
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&tscadc {
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status = "okay";
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tsc {
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ti,wires = <4>;
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ti,x-plate-resistance = <200>;
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ti,zx-cutoff-ratio = <40>;
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ti,min_deviation = <60>;
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ti,max_deviation = <600>;
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ti,coordinate-readouts = <5>;
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ti,wire-config = <0x00 0x11 0x22 0x33>;
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bnr-buttons {
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Home-Button {};
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};
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};
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adc {
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ti,adc-channels = <5 6 7>;
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};
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};
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&gpmc {
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u-boot,dm-spl;
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status = "okay";
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pinctrl-names = "default";
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ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
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nand@0,0 {
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compatible = "ti,omap2-nand";
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reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
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interrupt-parent = <&gpmc>;
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rb-gpios = <&gpmc 1 GPIO_ACTIVE_HIGH>; /* gpmc_wait1 */
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ti,nand-ecc-opt = "bch8";
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ti,elm-id = <&elm>;
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nand-bus-width = <8>;
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gpmc,device-width = <1>;
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gpmc,sync-clk-ps = <0>;
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gpmc,cs-on-ns = <0>;
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gpmc,cs-rd-off-ns = <44>;
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gpmc,cs-wr-off-ns = <44>;
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gpmc,adv-on-ns = <6>;
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gpmc,adv-rd-off-ns = <34>;
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gpmc,adv-wr-off-ns = <44>;
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gpmc,we-on-ns = <0>;
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gpmc,we-off-ns = <40>;
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gpmc,oe-on-ns = <0>;
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gpmc,oe-off-ns = <54>;
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gpmc,access-ns = <64>;
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gpmc,rd-cycle-ns = <82>;
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gpmc,wr-cycle-ns = <82>;
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gpmc,wait-on-read = "true";
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gpmc,wait-on-write = "true";
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gpmc,bus-turnaround-ns = <0>;
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gpmc,cycle2cycle-delay-ns = <0>;
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gpmc,clk-activation-ns = <0>;
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gpmc,wait-monitoring-ns = <0>;
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gpmc,wr-access-ns = <40>;
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gpmc,wr-data-mux-bus-ns = <0>;
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gpmc,wait-pin = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "NAND.MLO";
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reg = <0x00000000 0x000020000>;
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};
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partition@1 {
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label = "NAND.cfgscr";
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reg = <0x00020000 0x00020000>;
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};
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partition@2 {
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label = "NAND.dtb";
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reg = <0x00040000 0x00020000>;
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};
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partition@3 {
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label = "NAND.u-boot-env";
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reg = <0x00060000 0x00020000>;
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};
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partition@4 {
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label = "NAND.u-boot";
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reg = <0x00080000 0x00080000>;
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};
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partition@5 {
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label = "NAND.kernel";
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reg = <0x00100000 0x00400000>;
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};
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partition@6 {
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label = "NAND.rootfs";
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reg = <0x00500000 0x08000000>;
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};
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partition@7 {
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label = "NAND.user";
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reg = <0x08500000 0x17b00000>;
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};
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};
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};
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