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cd93d625fd
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
54 lines
1.8 KiB
C
54 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* K3: AM6 SoC definitions, structures etc.
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*
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* (C) Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
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*/
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#ifndef __ASM_ARCH_AM6_HARDWARE_H
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#define __ASM_ARCH_AM6_HARDWARE_H
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#include <config.h>
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#ifndef __ASSEMBLY__
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#include <linux/bitops.h>
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#endif
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#define CTRL_MMR0_BASE 0x00100000
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#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30)
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#define CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK GENMASK(3, 0)
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#define CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT 0
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#define CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK GENMASK(6, 4)
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#define CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT 4
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#define CTRLMMR_MAIN_DEVSTAT_MMC_PORT_MASK GENMASK(12, 12)
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#define CTRLMMR_MAIN_DEVSTAT_MMC_PORT_SHIFT 12
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#define CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_MASK GENMASK(14, 14)
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#define CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_SHIFT 14
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#define CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_MASK GENMASK(17, 17)
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#define CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT 12
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#define WKUP_CTRL_MMR0_BASE 0x43000000
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#define MCU_CTRL_MMR0_BASE 0x40f00000
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/*
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* The CTRL_MMR0 memory space is divided into several equally-spaced
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* partitions, so defining the partition size allows us to determine
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* register addresses common to those partitions.
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*/
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#define CTRL_MMR0_PARTITION_SIZE 0x4000
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/*
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* CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTR_MMR0 lock/kick-mechanism
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* shared register definitions.
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*/
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#define CTRLMMR_LOCK_KICK0 0x01008
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#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490
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#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0)
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#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0
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#define CTRLMMR_LOCK_KICK1 0x0100c
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#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a
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/* MCU SCRATCHPAD usage */
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#define TI_SRAM_SCRATCH_BOARD_EEPROM_START CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE
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#endif /* __ASM_ARCH_AM6_HARDWARE_H */
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