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739ba41d5a
The SC_* macros represent the address of SysCtrl registers. For a planned new SoC, its base address will be changed. Turn the SC_* macros into the offset from the base address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
119 lines
2.6 KiB
C
119 lines
2.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <linux/sizes.h>
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#include "../sc64-regs.h"
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#include "pll.h"
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/* PLL type: SSC */
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#define SC_PLLCTRL_SSC_DK_MASK GENMASK(14, 0)
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#define SC_PLLCTRL_SSC_EN BIT(31)
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#define SC_PLLCTRL2_NRSTDS BIT(28)
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#define SC_PLLCTRL2_SSC_JK_MASK GENMASK(26, 0)
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#define SC_PLLCTRL3_REGI_MASK GENMASK(19, 16)
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/* PLL type: VPLL27 */
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#define SC_VPLL27CTRL_WP BIT(0)
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#define SC_VPLL27CTRL3_K_LD BIT(28)
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/* PLL type: DSPLL */
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#define SC_DSPLLCTRL2_K_LD BIT(28)
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int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq,
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unsigned int ssc_rate, unsigned int divn)
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{
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void __iomem *base = sc_base + reg_base;
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u32 tmp;
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if (freq != UNIPHIER_PLL_FREQ_DEFAULT) {
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tmp = readl(base); /* SSCPLLCTRL */
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tmp &= ~SC_PLLCTRL_SSC_DK_MASK;
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tmp |= FIELD_PREP(SC_PLLCTRL_SSC_DK_MASK,
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DIV_ROUND_CLOSEST(487UL * freq * ssc_rate,
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divn * 512));
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writel(tmp, base);
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tmp = readl(base + 4);
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tmp &= ~SC_PLLCTRL2_SSC_JK_MASK;
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tmp |= FIELD_PREP(SC_PLLCTRL2_SSC_JK_MASK,
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DIV_ROUND_CLOSEST(21431887UL * freq,
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divn * 512));
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writel(tmp, base + 4);
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udelay(50);
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}
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tmp = readl(base + 4); /* SSCPLLCTRL2 */
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tmp |= SC_PLLCTRL2_NRSTDS;
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writel(tmp, base + 4);
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return 0;
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}
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int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base)
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{
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void __iomem *base = sc_base + reg_base;
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u32 tmp;
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tmp = readl(base); /* SSCPLLCTRL */
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tmp |= SC_PLLCTRL_SSC_EN;
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writel(tmp, base);
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return 0;
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}
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int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi)
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{
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void __iomem *base = sc_base + reg_base;
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u32 tmp;
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tmp = readl(base + 8); /* SSCPLLCTRL3 */
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tmp &= ~SC_PLLCTRL3_REGI_MASK;
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tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi);
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writel(tmp, base + 8);
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return 0;
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}
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int uniphier_ld20_vpll27_init(unsigned long reg_base)
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{
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void __iomem *base = sc_base + reg_base;
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u32 tmp;
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tmp = readl(base); /* VPLL27CTRL */
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tmp |= SC_VPLL27CTRL_WP; /* write protect off */
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writel(tmp, base);
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tmp = readl(base + 8); /* VPLL27CTRL3 */
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tmp |= SC_VPLL27CTRL3_K_LD;
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writel(tmp, base + 8);
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tmp = readl(base); /* VPLL27CTRL */
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tmp &= ~SC_VPLL27CTRL_WP; /* write protect on */
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writel(tmp, base);
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return 0;
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}
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int uniphier_ld20_dspll_init(unsigned long reg_base)
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{
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void __iomem *base = sc_base + reg_base;
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u32 tmp;
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tmp = readl(base + 4); /* DSPLLCTRL2 */
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tmp |= SC_DSPLLCTRL2_K_LD;
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writel(tmp, base + 4);
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return 0;
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}
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