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b4534ddeff
Port the mdio-mux-meson-gxl.c Linux driver introduced in [1],
and adapt it to U-Boot.
This driver is needed to boot U-Boot with Linux DT since v6.4,
since it switched the MDIO mux from the mmio to a proper GXL driver.
[1] 9a24e1ff4326 ("net: mdio: add amlogic gxl mdio mux support")
Link: https://lore.kernel.org/r/20231213-u-boot-gxl-mdio-mux-v2-1-c56bb02a75ea@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
139 lines
3.4 KiB
C
139 lines
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2022 Baylibre, SAS.
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* Author: Jerome Brunet <jbrunet@baylibre.com>
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* Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org>
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*/
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#include <dm.h>
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#include <errno.h>
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#include <log.h>
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#include <miiphy.h>
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#include <asm/io.h>
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#include <linux/bitfield.h>
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#include <linux/delay.h>
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#define ETH_REG2 0x0
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#define REG2_PHYID GENMASK(21, 0)
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#define EPHY_GXL_ID 0x110181
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#define REG2_LEDACT GENMASK(23, 22)
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#define REG2_LEDLINK GENMASK(25, 24)
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#define REG2_DIV4SEL BIT(27)
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#define REG2_ADCBYPASS BIT(30)
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#define REG2_CLKINSEL BIT(31)
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#define ETH_REG3 0x4
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#define REG3_ENH BIT(3)
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#define REG3_CFGMODE GENMASK(6, 4)
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#define REG3_AUTOMDIX BIT(7)
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#define REG3_PHYADDR GENMASK(12, 8)
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#define REG3_PWRUPRST BIT(21)
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#define REG3_PWRDOWN BIT(22)
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#define REG3_LEDPOL BIT(23)
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#define REG3_PHYMDI BIT(26)
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#define REG3_CLKINEN BIT(29)
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#define REG3_PHYIP BIT(30)
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#define REG3_PHYEN BIT(31)
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#define ETH_REG4 0x8
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#define REG4_PWRUPRSTSIG BIT(0)
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#define MESON_GXL_MDIO_EXTERNAL_ID 0
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#define MESON_GXL_MDIO_INTERNAL_ID 1
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struct mdio_mux_meson_gxl_priv {
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phys_addr_t regs;
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};
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static int meson_gxl_enable_internal_mdio(struct mdio_mux_meson_gxl_priv *priv)
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{
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u32 val;
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/* Setup the internal phy */
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val = (REG3_ENH |
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FIELD_PREP(REG3_CFGMODE, 0x7) |
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REG3_AUTOMDIX |
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FIELD_PREP(REG3_PHYADDR, 8) |
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REG3_LEDPOL |
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REG3_PHYMDI |
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REG3_CLKINEN |
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REG3_PHYIP);
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writel(REG4_PWRUPRSTSIG, priv->regs + ETH_REG4);
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writel(val, priv->regs + ETH_REG3);
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mdelay(10);
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/* NOTE: The HW kept the phy id configurable at runtime.
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* The id below is arbitrary. It is the one used in the vendor code.
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* The only constraint is that it must match the one in
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* drivers/net/phy/meson-gxl.c to properly match the PHY.
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*/
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writel(FIELD_PREP(REG2_PHYID, EPHY_GXL_ID),
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priv->regs + ETH_REG2);
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/* Enable the internal phy */
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val |= REG3_PHYEN;
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writel(val, priv->regs + ETH_REG3);
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writel(0, priv->regs + ETH_REG4);
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/* The phy needs a bit of time to power up */
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mdelay(10);
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return 0;
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}
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static int meson_gxl_enable_external_mdio(struct mdio_mux_meson_gxl_priv *priv)
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{
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/* Reset the mdio bus mux to the external phy */
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writel(0, priv->regs + ETH_REG3);
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return 0;
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}
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static int mdio_mux_meson_gxl_select(struct udevice *mux, int cur, int sel)
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{
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struct mdio_mux_meson_gxl_priv *priv = dev_get_priv(mux);
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debug("%s: %x -> %x\n", __func__, (u32)cur, (u32)sel);
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/* if last selection didn't change we're good to go */
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if (cur == sel)
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return 0;
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switch (sel) {
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case MESON_GXL_MDIO_EXTERNAL_ID:
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return meson_gxl_enable_external_mdio(priv);
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case MESON_GXL_MDIO_INTERNAL_ID:
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return meson_gxl_enable_internal_mdio(priv);
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default:
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return -EINVAL;
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}
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return 0;
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}
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static const struct mdio_mux_ops mdio_mux_meson_gxl_ops = {
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.select = mdio_mux_meson_gxl_select,
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};
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static int mdio_mux_meson_gxl_probe(struct udevice *dev)
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{
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struct mdio_mux_meson_gxl_priv *priv = dev_get_priv(dev);
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priv->regs = dev_read_addr(dev);
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return 0;
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}
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static const struct udevice_id mdio_mux_meson_gxl_ids[] = {
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{ .compatible = "amlogic,gxl-mdio-mux" },
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{ }
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};
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U_BOOT_DRIVER(mdio_mux_meson_gxl) = {
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.name = "mdio_mux_meson_gxl",
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.id = UCLASS_MDIO_MUX,
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.of_match = mdio_mux_meson_gxl_ids,
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.probe = mdio_mux_meson_gxl_probe,
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.ops = &mdio_mux_meson_gxl_ops,
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.priv_auto = sizeof(struct mdio_mux_meson_gxl_priv),
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};
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