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a836626cc4
The work-around for P4080 erratum SERDES9 says that the SERDES receiver lanes should be reset after the XAUI starts tranmitting alignment signals. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
234 lines
6.1 KiB
C
234 lines
6.1 KiB
C
/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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* Andy Fleming <afleming@freescale.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
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*/
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#ifndef _PHY_H
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#define _PHY_H
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#include <linux/list.h>
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#include <linux/mii.h>
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#include <linux/ethtool.h>
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#include <linux/mdio.h>
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#define PHY_MAX_ADDR 32
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#define PHY_BASIC_FEATURES (SUPPORTED_10baseT_Half | \
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SUPPORTED_10baseT_Full | \
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SUPPORTED_100baseT_Half | \
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SUPPORTED_100baseT_Full | \
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SUPPORTED_Autoneg | \
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SUPPORTED_TP | \
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SUPPORTED_MII)
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#define PHY_GBIT_FEATURES (PHY_BASIC_FEATURES | \
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SUPPORTED_1000baseT_Half | \
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SUPPORTED_1000baseT_Full)
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#define PHY_10G_FEATURES (PHY_GBIT_FEATURES | \
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SUPPORTED_10000baseT_Full)
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#define PHY_ANEG_TIMEOUT 4000
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typedef enum {
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PHY_INTERFACE_MODE_MII,
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PHY_INTERFACE_MODE_GMII,
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PHY_INTERFACE_MODE_SGMII,
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PHY_INTERFACE_MODE_TBI,
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PHY_INTERFACE_MODE_RMII,
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PHY_INTERFACE_MODE_RGMII,
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PHY_INTERFACE_MODE_RGMII_ID,
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PHY_INTERFACE_MODE_RGMII_RXID,
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PHY_INTERFACE_MODE_RGMII_TXID,
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PHY_INTERFACE_MODE_RTBI,
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PHY_INTERFACE_MODE_XGMII,
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PHY_INTERFACE_MODE_NONE /* Must be last */
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} phy_interface_t;
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static const char *phy_interface_strings[] = {
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[PHY_INTERFACE_MODE_MII] = "mii",
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[PHY_INTERFACE_MODE_GMII] = "gmii",
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[PHY_INTERFACE_MODE_SGMII] = "sgmii",
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[PHY_INTERFACE_MODE_TBI] = "tbi",
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[PHY_INTERFACE_MODE_RMII] = "rmii",
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[PHY_INTERFACE_MODE_RGMII] = "rgmii",
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[PHY_INTERFACE_MODE_RGMII_ID] = "rgmii-id",
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[PHY_INTERFACE_MODE_RGMII_RXID] = "rgmii-rxid",
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[PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid",
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[PHY_INTERFACE_MODE_RTBI] = "rtbi",
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[PHY_INTERFACE_MODE_XGMII] = "xgmii",
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[PHY_INTERFACE_MODE_NONE] = "",
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};
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static inline const char *phy_string_for_interface(phy_interface_t i)
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{
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/* Default to unknown */
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if (i > PHY_INTERFACE_MODE_NONE)
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i = PHY_INTERFACE_MODE_NONE;
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return phy_interface_strings[i];
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}
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struct phy_device;
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#define MDIO_NAME_LEN 32
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struct mii_dev {
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struct list_head link;
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char name[MDIO_NAME_LEN];
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void *priv;
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int (*read)(struct mii_dev *bus, int addr, int devad, int reg);
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int (*write)(struct mii_dev *bus, int addr, int devad, int reg,
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u16 val);
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int (*reset)(struct mii_dev *bus);
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struct phy_device *phymap[PHY_MAX_ADDR];
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u32 phy_mask;
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};
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/* struct phy_driver: a structure which defines PHY behavior
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*
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* uid will contain a number which represents the PHY. During
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* startup, the driver will poll the PHY to find out what its
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* UID--as defined by registers 2 and 3--is. The 32-bit result
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* gotten from the PHY will be masked to
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* discard any bits which may change based on revision numbers
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* unimportant to functionality
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*
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*/
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struct phy_driver {
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char *name;
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unsigned int uid;
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unsigned int mask;
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unsigned int mmds;
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u32 features;
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/* Called to do any driver startup necessities */
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/* Will be called during phy_connect */
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int (*probe)(struct phy_device *phydev);
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/* Called to configure the PHY, and modify the controller
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* based on the results. Should be called after phy_connect */
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int (*config)(struct phy_device *phydev);
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/* Called when starting up the controller */
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int (*startup)(struct phy_device *phydev);
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/* Called when bringing down the controller */
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int (*shutdown)(struct phy_device *phydev);
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struct list_head list;
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};
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struct phy_device {
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/* Information about the PHY type */
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/* And management functions */
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struct mii_dev *bus;
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struct phy_driver *drv;
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void *priv;
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struct eth_device *dev;
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/* forced speed & duplex (no autoneg)
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* partner speed & duplex & pause (autoneg)
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*/
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int speed;
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int duplex;
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/* The most recently read link state */
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int link;
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int port;
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phy_interface_t interface;
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u32 advertising;
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u32 supported;
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u32 mmds;
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int autoneg;
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int addr;
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int pause;
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int asym_pause;
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u32 phy_id;
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u32 flags;
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};
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static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
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{
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struct mii_dev *bus = phydev->bus;
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return bus->read(bus, phydev->addr, devad, regnum);
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}
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static inline int phy_write(struct phy_device *phydev, int devad, int regnum,
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u16 val)
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{
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struct mii_dev *bus = phydev->bus;
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return bus->write(bus, phydev->addr, devad, regnum, val);
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}
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#ifdef CONFIG_PHYLIB_10G
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extern struct phy_driver gen10g_driver;
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/* For now, XGMII is the only 10G interface */
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static inline int is_10g_interface(phy_interface_t interface)
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{
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return interface == PHY_INTERFACE_MODE_XGMII;
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}
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#endif
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int phy_init(void);
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int phy_reset(struct phy_device *phydev);
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struct phy_device *phy_connect(struct mii_dev *bus, int addr,
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struct eth_device *dev,
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phy_interface_t interface);
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int phy_startup(struct phy_device *phydev);
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int phy_config(struct phy_device *phydev);
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int phy_shutdown(struct phy_device *phydev);
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int phy_register(struct phy_driver *drv);
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int genphy_config_aneg(struct phy_device *phydev);
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int genphy_update_link(struct phy_device *phydev);
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int genphy_config(struct phy_device *phydev);
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int genphy_startup(struct phy_device *phydev);
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int genphy_shutdown(struct phy_device *phydev);
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int gen10g_config(struct phy_device *phydev);
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int gen10g_startup(struct phy_device *phydev);
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int gen10g_shutdown(struct phy_device *phydev);
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int gen10g_discover_mmds(struct phy_device *phydev);
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int phy_atheros_init(void);
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int phy_broadcom_init(void);
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int phy_davicom_init(void);
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int phy_lxt_init(void);
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int phy_marvell_init(void);
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int phy_micrel_init(void);
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int phy_natsemi_init(void);
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int phy_realtek_init(void);
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int phy_teranetics_init(void);
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int phy_vitesse_init(void);
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/* PHY UIDs for various PHYs that are referenced in external code */
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#define PHY_UID_TN2020 0x00a19410
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#endif
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