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8a8d24bdf1
Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
91 lines
1.6 KiB
C
91 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2016 Google, Inc
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*
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* From Coreboot src/soc/intel/broadwell/include/soc/gpio.h
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*/
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#ifndef __ASM_ARCH_GPIO
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#define __ASM_ARCH_GPIO
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#define GPIO_PER_BANK 32
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#define GPIO_BANKS 3
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struct broadwell_bank_plat {
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uint16_t base_addr;
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const char *bank_name;
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int bank;
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};
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/* PCH-LP GPIOBASE Registers */
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struct pch_lp_gpio_regs {
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u32 own[GPIO_BANKS];
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u32 reserved0;
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u16 pirq_to_ioxapic;
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u16 reserved1[3];
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u32 blink;
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u32 ser_blink;
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u32 ser_blink_cmdsts;
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u32 ser_blink_data;
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u16 gpi_nmi_en;
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u16 gpi_nmi_sts;
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u32 reserved2;
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u32 gpi_route[GPIO_BANKS];
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u32 reserved3;
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u32 reserved4[4];
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u32 alt_gpi_smi_sts;
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u32 alt_gpi_smi_en;
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u32 reserved5[2];
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u32 rst_sel[GPIO_BANKS];
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u32 reserved6;
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u32 reserved9[3];
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u32 gpio_gc;
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u32 gpi_is[GPIO_BANKS];
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u32 reserved10;
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u32 gpi_ie[GPIO_BANKS];
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u32 reserved11;
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u32 reserved12[24];
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struct {
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u32 conf_a;
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u32 conf_b;
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} config[GPIO_BANKS * GPIO_PER_BANK];
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};
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check_member(pch_lp_gpio_regs, gpi_ie[0], 0x90);
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check_member(pch_lp_gpio_regs, config[0], 0x100);
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enum {
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CONFA_MODE_SHIFT = 0,
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CONFA_MODE_GPIO = 1 << CONFA_MODE_SHIFT,
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CONFA_DIR_SHIFT = 2,
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CONFA_DIR_INPUT = 1 << CONFA_DIR_SHIFT,
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CONFA_INVERT_SHIFT = 3,
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CONFA_INVERT = 1 << CONFA_INVERT_SHIFT,
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CONFA_TRIGGER_SHIFT = 4,
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CONFA_TRIGGER_LEVEL = 1 << CONFA_TRIGGER_SHIFT,
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CONFA_LEVEL_SHIFT = 30,
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CONFA_LEVEL_HIGH = 1UL << CONFA_LEVEL_SHIFT,
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CONFA_OUTPUT_SHIFT = 31,
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CONFA_OUTPUT_HIGH = 1UL << CONFA_OUTPUT_SHIFT,
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CONFB_SENSE_SHIFT = 2,
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CONFB_SENSE_DISABLE = 1 << CONFB_SENSE_SHIFT,
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};
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#endif
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