mirror of
https://github.com/smaeul/u-boot.git
synced 2025-11-04 05:50:17 +00:00
d12618b927
Add the board support for the i.MX8MM Cloos PHG board. This board uses a imx8mm-tqma8mqml SoM from TQ-Group. imx8mm-phg.dts and imx8mm-tqma8mqml.dtsi are taken directly from Linux 6.2-rc3. Signed-off-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
148 lines
2.8 KiB
C
148 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* Copyright 2019 NXP
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <command.h>
|
|
#include <cpu_func.h>
|
|
#include <hang.h>
|
|
#include <image.h>
|
|
#include <init.h>
|
|
#include <log.h>
|
|
#include <spl.h>
|
|
#include <asm/global_data.h>
|
|
#include <asm/io.h>
|
|
#include <asm/mach-imx/iomux-v3.h>
|
|
#include <asm/arch/clock.h>
|
|
#include <asm/arch/imx8mm_pins.h>
|
|
#include <asm/arch/sys_proto.h>
|
|
#include <asm/mach-imx/boot_mode.h>
|
|
#include <asm/arch/ddr.h>
|
|
|
|
#include <dm/uclass.h>
|
|
#include <dm/device.h>
|
|
#include <dm/uclass-internal.h>
|
|
#include <dm/device-internal.h>
|
|
|
|
#include <power/pmic.h>
|
|
#include <power/pca9450.h>
|
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
int spl_board_boot_device(enum boot_device boot_dev_spl)
|
|
{
|
|
switch (boot_dev_spl) {
|
|
case USB_BOOT:
|
|
return BOOT_DEVICE_BOARD;
|
|
case SD2_BOOT:
|
|
case MMC2_BOOT:
|
|
return BOOT_DEVICE_MMC1;
|
|
case SD3_BOOT:
|
|
case MMC3_BOOT:
|
|
return BOOT_DEVICE_MMC2;
|
|
default:
|
|
return BOOT_DEVICE_NONE;
|
|
}
|
|
}
|
|
|
|
static void spl_dram_init(void)
|
|
{
|
|
ddr_init(&dram_timing);
|
|
}
|
|
|
|
void spl_board_init(void)
|
|
{
|
|
if (is_usb_boot())
|
|
puts("USB Boot\n");
|
|
else
|
|
puts("Normal Boot\n");
|
|
}
|
|
|
|
#ifdef CONFIG_SPL_LOAD_FIT
|
|
int board_fit_config_name_match(const char *name)
|
|
{
|
|
/* Just empty function now - can't decide what to choose */
|
|
debug("%s: %s\n", __func__, name);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static int power_init_board(void)
|
|
{
|
|
struct udevice *dev;
|
|
int ret;
|
|
|
|
ret = pmic_get("pmic@25", &dev);
|
|
if (ret == -ENODEV) {
|
|
puts("No pmic\n");
|
|
return 0;
|
|
}
|
|
if (ret != 0)
|
|
return ret;
|
|
|
|
/* BUCKxOUT_DVS0/1 control BUCK123 output */
|
|
pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
|
|
|
|
/* Buck 1 DVS control through PMIC_STBY_REQ */
|
|
pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
|
|
|
|
/* Set DVS1 to 0.8V for suspend */
|
|
pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x10);
|
|
|
|
/* increase VDD_DRAM to 0.95V for 3GHz DDR */
|
|
pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1C);
|
|
|
|
/* VDD_DRAM needs off in suspend, set B1_ENMODE=10 (ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L) */
|
|
pmic_reg_write(dev, PCA9450_BUCK3CTRL, 0x4a);
|
|
|
|
/* set VDD_SNVS_0V8 from default 0.85V */
|
|
pmic_reg_write(dev, PCA9450_LDO2CTRL, 0xC0);
|
|
|
|
/* set WDOG_B_CFG to cold reset */
|
|
pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void board_init_f(ulong dummy)
|
|
{
|
|
struct udevice *dev;
|
|
int ret;
|
|
|
|
arch_cpu_init();
|
|
|
|
init_uart_clk(1);
|
|
|
|
timer_init();
|
|
|
|
/* Clear the BSS. */
|
|
memset(__bss_start, 0, __bss_end - __bss_start);
|
|
|
|
ret = spl_early_init();
|
|
if (ret) {
|
|
debug("spl_early_init() failed: %d\n", ret);
|
|
hang();
|
|
}
|
|
|
|
ret = uclass_get_device_by_name(UCLASS_CLK,
|
|
"clock-controller@30380000",
|
|
&dev);
|
|
if (ret < 0) {
|
|
printf("Failed to find clock node. Check device tree\n");
|
|
hang();
|
|
}
|
|
|
|
preloader_console_init();
|
|
|
|
enable_tzc380();
|
|
|
|
power_init_board();
|
|
|
|
/* DDR initialization */
|
|
spl_dram_init();
|
|
|
|
board_init_r(NULL, 0);
|
|
}
|