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1fc2329121
Systems such as Apple's M1 and M2 SoCs may have separate IOMMUs for each PCIe root port. In this case the right IOMMU for a PCI device behind a particular root port is described by an "iommu-map" property in the device tree. Parse this property and use it to find the right IOMMU device for PCI devices. Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
139 lines
2.9 KiB
C
139 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2021 Mark Kettenis <kettenis@openbsd.org>
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*/
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#define LOG_CATEGORY UCLASS_IOMMU
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#include <common.h>
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#include <dm.h>
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#include <iommu.h>
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#include <malloc.h>
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#include <phys2bus.h>
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#include <asm/io.h>
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#if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA))
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#if CONFIG_IS_ENABLED(PCI)
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static int dev_pci_iommu_enable(struct udevice *dev)
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{
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struct udevice *parent = dev->parent;
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struct udevice *dev_iommu;
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u32 *iommu_map;
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u32 iommu_map_mask, length, phandle, rid, rid_base;
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int i, count, len, ret;
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while (parent) {
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len = dev_read_size(parent, "iommu-map");
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if (len > 0)
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break;
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parent = parent->parent;
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}
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if (len <= 0)
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return 0;
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iommu_map = malloc(len);
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if (!iommu_map)
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return -ENOMEM;
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count = len / sizeof(u32);
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ret = dev_read_u32_array(parent, "iommu-map", iommu_map, count);
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if (ret < 0) {
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free(iommu_map);
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return 0;
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}
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iommu_map_mask = dev_read_u32_default(parent, "iommu-map-mask", ~0);
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rid = (dm_pci_get_bdf(dev) >> 8) & iommu_map_mask;
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/* Loop over entries until mapping is found. */
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for (i = 0; i < count; i += 4) {
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rid_base = iommu_map[i];
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phandle = iommu_map[i + 1];
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length = iommu_map[i + 3];
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if (rid < rid_base || rid >= rid_base + length)
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continue;
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ret = uclass_get_device_by_phandle_id(UCLASS_IOMMU, phandle,
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&dev_iommu);
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if (ret) {
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debug("%s: uclass_get_device_by_ofnode failed: %d\n",
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__func__, ret);
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free(iommu_map);
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return ret;
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}
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dev->iommu = dev_iommu;
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break;
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}
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free(iommu_map);
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return 0;
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}
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#endif
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int dev_iommu_enable(struct udevice *dev)
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{
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struct ofnode_phandle_args args;
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struct udevice *dev_iommu;
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int i, count, ret = 0;
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count = dev_count_phandle_with_args(dev, "iommus",
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"#iommu-cells", 0);
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for (i = 0; i < count; i++) {
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ret = dev_read_phandle_with_args(dev, "iommus",
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"#iommu-cells", 0, i, &args);
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if (ret) {
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debug("%s: dev_read_phandle_with_args failed: %d\n",
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__func__, ret);
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return ret;
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}
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ret = uclass_get_device_by_ofnode(UCLASS_IOMMU, args.node,
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&dev_iommu);
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if (ret) {
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debug("%s: uclass_get_device_by_ofnode failed: %d\n",
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__func__, ret);
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return ret;
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}
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dev->iommu = dev_iommu;
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}
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if (CONFIG_IS_ENABLED(PCI) && count < 0 &&
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device_is_on_pci_bus(dev))
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return dev_pci_iommu_enable(dev);
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return 0;
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}
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#endif
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dma_addr_t dev_iommu_dma_map(struct udevice *dev, void *addr, size_t size)
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{
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const struct iommu_ops *ops;
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if (dev->iommu) {
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ops = device_get_ops(dev->iommu);
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if (ops && ops->map)
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return ops->map(dev->iommu, addr, size);
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}
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return dev_phys_to_bus(dev, virt_to_phys(addr));
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}
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void dev_iommu_dma_unmap(struct udevice *dev, dma_addr_t addr, size_t size)
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{
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const struct iommu_ops *ops;
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if (dev->iommu) {
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ops = device_get_ops(dev->iommu);
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if (ops && ops->unmap)
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ops->unmap(dev->iommu, addr, size);
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}
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}
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UCLASS_DRIVER(iommu) = {
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.id = UCLASS_IOMMU,
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.name = "iommu",
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};
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