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6756762024
Fix the offset of TCNT0 register, which is 0xc on SH4. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
17 lines
347 B
C
17 lines
347 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2009 Freescale Semiconductor, Inc.
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*/
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#ifndef _ASM_CONFIG_H_
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#define _ASM_CONFIG_H_
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#include <asm/processor.h>
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/* Timer */
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#define CONFIG_SYS_TIMER_COUNTS_DOWN
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#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */
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#define CONFIG_SYS_TIMER_RATE (CONFIG_SYS_CLK_FREQ / 4)
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#endif
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