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9b4d52b2e1
Fix model name, node locations and also add pinctrl description for usb. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/3295fde73db13a712b65f4967eb5f39ced895ad4.1679988091.git.michal.simek@amd.com
98 lines
1.4 KiB
Plaintext
98 lines
1.4 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Xilinx MicroZED board DTS
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*
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* Copyright (C) 2013 - 2016 Xilinx, Inc.
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*/
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/dts-v1/;
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#include "zynq-7000.dtsi"
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/ {
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model = "Avnet MicroZed board";
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compatible = "avnet,zynq-microzed", "xlnx,zynq-microzed", "xlnx,zynq-7000";
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aliases {
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serial0 = &uart1;
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spi0 = &qspi;
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mmc0 = &sdhci0;
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x40000000>;
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};
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chosen {
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bootargs = "earlycon";
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stdout-path = "serial0:115200n8";
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};
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usb_phy0: phy0 {
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compatible = "usb-nop-xceiv";
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#phy-cells = <0>;
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};
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};
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&clkc {
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ps-clk-frequency = <33333333>;
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};
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&qspi {
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bootph-all;
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status = "okay";
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};
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&gem0 {
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status = "okay";
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phy-mode = "rgmii-id";
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phy-handle = <ðernet_phy>;
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ethernet_phy: ethernet-phy@0 {
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reg = <0>;
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};
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};
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&sdhci0 {
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bootph-all;
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status = "okay";
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};
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&uart1 {
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bootph-all;
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status = "okay";
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};
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&usb0 {
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status = "okay";
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dr_mode = "host";
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usb-phy = <&usb_phy0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb0_default>;
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};
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&pinctrl0 {
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pinctrl_usb0_default: usb0-default {
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mux {
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groups = "usb0_0_grp";
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function = "usb0";
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};
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conf {
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groups = "usb0_0_grp";
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slew-rate = <0>;
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io-standard = <1>;
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};
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conf-rx {
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pins = "MIO29", "MIO31", "MIO36";
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bias-high-impedance;
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};
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conf-tx {
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pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
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"MIO35", "MIO37", "MIO38", "MIO39";
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bias-disable;
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};
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};
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};
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